| Message ID | 20200203144716.32204-10-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Implement PAN, ATS1E1, UAO | expand |
On Mon, 3 Feb 2020 at 14:47, Richard Henderson <richard.henderson@linaro.org> wrote: > > The CPSR_USER mask for IS_USER already avoids all of the RES0 > bits as per aarch32_cpsr_valid_mask. Fix up the formatting. CPSR_USER includes CPSR_Q and CPSR_GE, which might be RES0 depending on feature bit settings. Diff made a bit of a mess of this patch -- I think it would be easier to understand if the reformatting to add {} was separate from the code change. thanks -- PMM
On 2/7/20 5:40 PM, Peter Maydell wrote: > On Mon, 3 Feb 2020 at 14:47, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> The CPSR_USER mask for IS_USER already avoids all of the RES0 >> bits as per aarch32_cpsr_valid_mask. Fix up the formatting. > > CPSR_USER includes CPSR_Q and CPSR_GE, which might be RES0 > depending on feature bit settings. Oops, yes. > Diff made a bit of a mess of this patch -- I think it would > be easier to understand if the reformatting to add {} was > separate from the code change. Because of the above, I'll probably drop all of this except for the formatting fix. r~
diff --git a/target/arm/translate.c b/target/arm/translate.c index 032f7074cb..2b3bfcf7ca 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2734,28 +2734,34 @@ static inline void gen_mulxy(TCGv_i32 t0, TCGv_i32 t1, int x, int y) /* Return the mask of PSR bits set by a MSR instruction. */ static uint32_t msr_mask(DisasContext *s, int flags, int spsr) { - uint32_t mask; + uint32_t mask = 0; - mask = 0; - if (flags & (1 << 0)) + if (flags & (1 << 0)) { mask |= 0xff; - if (flags & (1 << 1)) - mask |= 0xff00; - if (flags & (1 << 2)) - mask |= 0xff0000; - if (flags & (1 << 3)) - mask |= 0xff000000; - - /* Mask out undefined bits. */ - mask &= aarch32_cpsr_valid_mask(s->features, s->isar); - - /* Mask out execution state and reserved bits. */ - if (!spsr) { - mask &= ~CPSR_EXEC; } - /* Mask out privileged bits. */ - if (IS_USER(s)) + if (flags & (1 << 1)) { + mask |= 0xff00; + } + if (flags & (1 << 2)) { + mask |= 0xff0000; + } + if (flags & (1 << 3)) { + mask |= 0xff000000; + } + + if (IS_USER(s)) { + /* Mask out privileged bits. */ mask &= CPSR_USER; + } else { + /* Mask out undefined bits. */ + mask &= aarch32_cpsr_valid_mask(s->features, s->isar); + + /* Mask out execution state and reserved bits. */ + if (!spsr) { + mask &= ~CPSR_EXEC; + } + } + return mask; }
The CPSR_USER mask for IS_USER already avoids all of the RES0 bits as per aarch32_cpsr_valid_mask. Fix up the formatting. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/translate.c | 42 ++++++++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 18 deletions(-)