| Message ID | 20200120034937.128600-3-jian.hu@amlogic.com (mailing list archive) |
|---|---|
| State | New, archived |
| Delegated to: | Neil Armstrong |
| Headers | show |
| Series | add Amlogic A1 clock controller driver | expand |
On Mon 20 Jan 2020 at 04:49, Jian Hu <jian.hu@amlogic.com> wrote: > Compared with the previous SoCs, self-adaption current module > is newly added for A1, and there is no reset parm except the > fixed pll. In A1 PLL, the PLL enable sequence is different, using > the new power-on sequence to enable the PLL. Things are getting clearer thanks to Martin's suggestions and I can understand what your driver is doing now However, I still have a problem with the fact that 2 different pll types are getting intertwined in this driver. Parameters mandatory to one is made optional to the other. Nothing clearly shows which needs what and the combinatorial are quickly growing. Apparently the only real difference is in enable/disable, So I would prefer if the a1 had dedicated function for these ops. I suppose you'll have to submit clk_hw_enable() and clk_hw_disable() to the framework to call the appropriate ops dependind on the SoC. > > Signed-off-by: Jian Hu <jian.hu@amlogic.com> > Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > --- > drivers/clk/meson/clk-pll.c | 47 +++++++++++++++++++++++++++++++------ > drivers/clk/meson/clk-pll.h | 2 ++ > 2 files changed, 42 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c > index ddb1e5634739..10926291440f 100644 > --- a/drivers/clk/meson/clk-pll.c > +++ b/drivers/clk/meson/clk-pll.c > @@ -283,10 +283,14 @@ static void meson_clk_pll_init(struct clk_hw *hw) > struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); > > if (pll->init_count) { > - meson_parm_write(clk->map, &pll->rst, 1); > + if (MESON_PARM_APPLICABLE(&pll->rst)) > + meson_parm_write(clk->map, &pll->rst, 1); > + replace by enabled = clk_hw_is_enabled(hw) if (enabled) clk_hw_disable(hw) > regmap_multi_reg_write(clk->map, pll->init_regs, > pll->init_count); > - meson_parm_write(clk->map, &pll->rst, 0); > + > + if (MESON_PARM_APPLICABLE(&pll->rst)) > + meson_parm_write(clk->map, &pll->rst, 0); /* restore if necessary */ if (enabled) clk_hw_enable(hw) > } > } > > @@ -295,8 +299,11 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) > struct clk_regmap *clk = to_clk_regmap(hw); > struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); > > - if (meson_parm_read(clk->map, &pll->rst) || > - !meson_parm_read(clk->map, &pll->en) || > + if (MESON_PARM_APPLICABLE(&pll->rst) && > + meson_parm_read(clk->map, &pll->rst)) > + return 0; > + > + if (!meson_parm_read(clk->map, &pll->en) || > !meson_parm_read(clk->map, &pll->l)) > return 0; I suppose the pll can't be locked if it was in reset, so we could drop the check on `rst` entirely to simplify the function > > @@ -323,13 +330,34 @@ static int meson_clk_pll_enable(struct clk_hw *hw) > return 0; > > /* Make sure the pll is in reset */ > - meson_parm_write(clk->map, &pll->rst, 1); > + if (MESON_PARM_APPLICABLE(&pll->rst)) > + meson_parm_write(clk->map, &pll->rst, 1); > > /* Enable the pll */ > meson_parm_write(clk->map, &pll->en, 1); > > /* Take the pll out reset */ > - meson_parm_write(clk->map, &pll->rst, 0); > + if (MESON_PARM_APPLICABLE(&pll->rst)) > + meson_parm_write(clk->map, &pll->rst, 0); > + > + /* > + * Compared with the previous SoCs, self-adaption current module > + * is newly added for A1, keep the new power-on sequence to enable the > + * PLL. The sequence is: > + * 1. enable the pll, delay for 10us > + * 2. enable the pll self-adaption current module, delay for 40us > + * 3. enable the lock detect module > + */ > + if (MESON_PARM_APPLICABLE(&pll->current_en)) { > + udelay(10); > + meson_parm_write(clk->map, &pll->current_en, 1); > + udelay(40); > + }; > + > + if (MESON_PARM_APPLICABLE(&pll->l_detect)) { > + meson_parm_write(clk->map, &pll->l_detect, 1); > + meson_parm_write(clk->map, &pll->l_detect, 0); > + } > > if (meson_clk_pll_wait_lock(hw)) > return -EIO; > @@ -343,10 +371,15 @@ static void meson_clk_pll_disable(struct clk_hw *hw) > struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); > > /* Put the pll is in reset */ > - meson_parm_write(clk->map, &pll->rst, 1); > + if (MESON_PARM_APPLICABLE(&pll->rst)) > + meson_parm_write(clk->map, &pll->rst, 1); > > /* Disable the pll */ > meson_parm_write(clk->map, &pll->en, 0); > + > + /* Disable PLL internal self-adaption current module */ > + if (MESON_PARM_APPLICABLE(&pll->current_en)) > + meson_parm_write(clk->map, &pll->current_en, 0); > } With the above clarified, it should be easy to properly split the functions between the legacy type and the a1 type. You'll need to update meson_clk_pll_set_rate() to call - clk_hw_is_enabled() - clk_hw_enable() and clk_hw_disable() (again, you'll need to add those in the framework first) > > static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, > diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h > index 367efd0f6410..a2228c0fdce5 100644 > --- a/drivers/clk/meson/clk-pll.h > +++ b/drivers/clk/meson/clk-pll.h > @@ -36,6 +36,8 @@ struct meson_clk_pll_data { > struct parm frac; > struct parm l; > struct parm rst; > + struct parm current_en; > + struct parm l_detect; > const struct reg_sequence *init_regs; > unsigned int init_count; > const struct pll_params_table *table;
Hi Jerome Thanks for your suggestions. On 2020/2/4 18:24, Jerome Brunet wrote: > > On Mon 20 Jan 2020 at 04:49, Jian Hu <jian.hu@amlogic.com> wrote: > >> Compared with the previous SoCs, self-adaption current module >> is newly added for A1, and there is no reset parm except the >> fixed pll. In A1 PLL, the PLL enable sequence is different, using >> the new power-on sequence to enable the PLL. > > Things are getting clearer thanks to Martin's suggestions and I can > understand what your driver is doing now > > However, I still have a problem with the fact that 2 different pll types > are getting intertwined in this driver. Parameters mandatory to one is > made optional to the other. Nothing clearly shows which needs what and > the combinatorial are quickly growing. > > Apparently the only real difference is in enable/disable, So I would > prefer if the a1 had dedicated function for these ops. > > I suppose you'll have to submit clk_hw_enable() and clk_hw_disable() > to the framework to call the appropriate ops dependind on the SoC. > I am confused here. What does clk_hw_is_enabled/clk_hw_enable/clk_hw_disable use here? clk_hw_is_enabled is intend to check a parm's existence? But clk_hw_is_enabled which is existed in CCF to check a PLL is locked or not. Maybe I understand wrong about your suggestions. Could you list a example for clk_hw_enable and clk_hw_disable function implementation? >> >> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> >> --- >> drivers/clk/meson/clk-pll.c | 47 +++++++++++++++++++++++++++++++------ >> drivers/clk/meson/clk-pll.h | 2 ++ >> 2 files changed, 42 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c >> index ddb1e5634739..10926291440f 100644 >> --- a/drivers/clk/meson/clk-pll.c >> +++ b/drivers/clk/meson/clk-pll.c >> @@ -283,10 +283,14 @@ static void meson_clk_pll_init(struct clk_hw *hw) >> struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); >> >> if (pll->init_count) { >> - meson_parm_write(clk->map, &pll->rst, 1); >> + if (MESON_PARM_APPLICABLE(&pll->rst)) >> + meson_parm_write(clk->map, &pll->rst, 1); >> + > > replace by > enabled = clk_hw_is_enabled(hw) > if (enabled) > clk_hw_disable(hw) > clk_hw_is_enabled here is used to check 'pll->rst'? >> regmap_multi_reg_write(clk->map, pll->init_regs, >> pll->init_count); >> - meson_parm_write(clk->map, &pll->rst, 0); >> + >> + if (MESON_PARM_APPLICABLE(&pll->rst)) >> + meson_parm_write(clk->map, &pll->rst, 0); > > /* restore if necessary */ > if (enabled) > clk_hw_enable(hw) > >> } >> } >> >> @@ -295,8 +299,11 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) >> struct clk_regmap *clk = to_clk_regmap(hw); >> struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); >> >> - if (meson_parm_read(clk->map, &pll->rst) || >> - !meson_parm_read(clk->map, &pll->en) || >> + if (MESON_PARM_APPLICABLE(&pll->rst) && >> + meson_parm_read(clk->map, &pll->rst)) >> + return 0; >> + >> + if (!meson_parm_read(clk->map, &pll->en) || >> !meson_parm_read(clk->map, &pll->l)) >> return 0; > > I suppose the pll can't be locked if it was in reset, so we could drop > the check on `rst` entirely to simplify the function > OK, I will drop 'rst' check. >> >> @@ -323,13 +330,34 @@ static int meson_clk_pll_enable(struct clk_hw *hw) >> return 0; >> >> /* Make sure the pll is in reset */ >> - meson_parm_write(clk->map, &pll->rst, 1); >> + if (MESON_PARM_APPLICABLE(&pll->rst)) >> + meson_parm_write(clk->map, &pll->rst, 1); >> >> /* Enable the pll */ >> meson_parm_write(clk->map, &pll->en, 1); >> >> /* Take the pll out reset */ >> - meson_parm_write(clk->map, &pll->rst, 0); >> + if (MESON_PARM_APPLICABLE(&pll->rst)) >> + meson_parm_write(clk->map, &pll->rst, 0); >> + >> + /* >> + * Compared with the previous SoCs, self-adaption current module >> + * is newly added for A1, keep the new power-on sequence to enable the >> + * PLL. The sequence is: >> + * 1. enable the pll, delay for 10us >> + * 2. enable the pll self-adaption current module, delay for 40us >> + * 3. enable the lock detect module >> + */ >> + if (MESON_PARM_APPLICABLE(&pll->current_en)) { >> + udelay(10); >> + meson_parm_write(clk->map, &pll->current_en, 1); >> + udelay(40); >> + }; >> + >> + if (MESON_PARM_APPLICABLE(&pll->l_detect)) { >> + meson_parm_write(clk->map, &pll->l_detect, 1); >> + meson_parm_write(clk->map, &pll->l_detect, 0); >> + } >> >> if (meson_clk_pll_wait_lock(hw)) >> return -EIO; >> @@ -343,10 +371,15 @@ static void meson_clk_pll_disable(struct clk_hw *hw) >> struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); >> >> /* Put the pll is in reset */ >> - meson_parm_write(clk->map, &pll->rst, 1); >> + if (MESON_PARM_APPLICABLE(&pll->rst)) >> + meson_parm_write(clk->map, &pll->rst, 1); >> >> /* Disable the pll */ >> meson_parm_write(clk->map, &pll->en, 0); >> + >> + /* Disable PLL internal self-adaption current module */ >> + if (MESON_PARM_APPLICABLE(&pll->current_en)) >> + meson_parm_write(clk->map, &pll->current_en, 0); >> } > > With the above clarified, it should be easy to properly split the > functions between the legacy type and the a1 type. > > You'll need to update meson_clk_pll_set_rate() to call > - clk_hw_is_enabled() > - clk_hw_enable() and clk_hw_disable() (again, you'll need to add > those in the framework first) > >> >> static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, >> diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h >> index 367efd0f6410..a2228c0fdce5 100644 >> --- a/drivers/clk/meson/clk-pll.h >> +++ b/drivers/clk/meson/clk-pll.h >> @@ -36,6 +36,8 @@ struct meson_clk_pll_data { >> struct parm frac; >> struct parm l; >> struct parm rst; >> + struct parm current_en; >> + struct parm l_detect; >> const struct reg_sequence *init_regs; >> unsigned int init_count; >> const struct pll_params_table *table; > > . >
On Mon 10 Feb 2020 at 07:11, Jian Hu <jian.hu@amlogic.com> wrote: > Hi Jerome > > Thanks for your suggestions. > > On 2020/2/4 18:24, Jerome Brunet wrote: >> >> On Mon 20 Jan 2020 at 04:49, Jian Hu <jian.hu@amlogic.com> wrote: >> >>> Compared with the previous SoCs, self-adaption current module >>> is newly added for A1, and there is no reset parm except the >>> fixed pll. In A1 PLL, the PLL enable sequence is different, using >>> the new power-on sequence to enable the PLL. >> >> Things are getting clearer thanks to Martin's suggestions and I can >> understand what your driver is doing now >> >> However, I still have a problem with the fact that 2 different pll types >> are getting intertwined in this driver. Parameters mandatory to one is >> made optional to the other. Nothing clearly shows which needs what and >> the combinatorial are quickly growing. >> >> Apparently the only real difference is in enable/disable, So I would >> prefer if the a1 had dedicated function for these ops. >> >> I suppose you'll have to submit clk_hw_enable() and clk_hw_disable() >> to the framework to call the appropriate ops dependind on the SoC. >> > I am confused here. > What does clk_hw_is_enabled/clk_hw_enable/clk_hw_disable use here? I'm asking you to make different callback for .enable() and .disable(). The .set_rate() callback of this driver needs to turn off and on the clock, so it needs to call the appropriate one. To do so, you should go through a clk_hw_xxxxx() function. > > clk_hw_is_enabled is intend to check a parm's existence? But > clk_hw_is_enabled which is existed in CCF to check a PLL is locked or > not. Maybe I understand wrong about your suggestions. > > Could you list a example for clk_hw_enable and clk_hw_disable function > implementation? drivers/clk/clk.c:523 : clk_hw_is_enabled() clk_hw_enable() and clk_hw_disable() so you'll need to implement these one and submit them. >>> >>> Signed-off-by: Jian Hu <jian.hu@amlogic.com> >>> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> >>> --- >>> drivers/clk/meson/clk-pll.c | 47 +++++++++++++++++++++++++++++++------ >>> drivers/clk/meson/clk-pll.h | 2 ++ >>> 2 files changed, 42 insertions(+), 7 deletions(-) >>> >>> diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c >>> index ddb1e5634739..10926291440f 100644 >>> --- a/drivers/clk/meson/clk-pll.c >>> +++ b/drivers/clk/meson/clk-pll.c >>> @@ -283,10 +283,14 @@ static void meson_clk_pll_init(struct clk_hw *hw) >>> struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); >>> if (pll->init_count) { >>> - meson_parm_write(clk->map, &pll->rst, 1); >>> + if (MESON_PARM_APPLICABLE(&pll->rst)) >>> + meson_parm_write(clk->map, &pll->rst, 1); >>> + >> >> replace by >> enabled = clk_hw_is_enabled(hw) >> if (enabled) >> clk_hw_disable(hw) >> > clk_hw_is_enabled here is used to check 'pll->rst'? >>> regmap_multi_reg_write(clk->map, pll->init_regs, >>> pll->init_count); >>> - meson_parm_write(clk->map, &pll->rst, 0); >>> + >>> + if (MESON_PARM_APPLICABLE(&pll->rst)) >>> + meson_parm_write(clk->map, &pll->rst, 0); >> >> /* restore if necessary */ >> if (enabled) >> clk_hw_enable(hw) >> >>> } >>> } >>> @@ -295,8 +299,11 @@ static int meson_clk_pll_is_enabled(struct clk_hw >>> *hw) >>> struct clk_regmap *clk = to_clk_regmap(hw); >>> struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); >>> - if (meson_parm_read(clk->map, &pll->rst) || >>> - !meson_parm_read(clk->map, &pll->en) || >>> + if (MESON_PARM_APPLICABLE(&pll->rst) && >>> + meson_parm_read(clk->map, &pll->rst)) >>> + return 0; >>> + >>> + if (!meson_parm_read(clk->map, &pll->en) || >>> !meson_parm_read(clk->map, &pll->l)) >>> return 0; >> >> I suppose the pll can't be locked if it was in reset, so we could drop >> the check on `rst` entirely to simplify the function >> > OK, I will drop 'rst' check. >>> @@ -323,13 +330,34 @@ static int meson_clk_pll_enable(struct clk_hw >>> *hw) >>> return 0; >>> /* Make sure the pll is in reset */ >>> - meson_parm_write(clk->map, &pll->rst, 1); >>> + if (MESON_PARM_APPLICABLE(&pll->rst)) >>> + meson_parm_write(clk->map, &pll->rst, 1); >>> /* Enable the pll */ >>> meson_parm_write(clk->map, &pll->en, 1); >>> /* Take the pll out reset */ >>> - meson_parm_write(clk->map, &pll->rst, 0); >>> + if (MESON_PARM_APPLICABLE(&pll->rst)) >>> + meson_parm_write(clk->map, &pll->rst, 0); >>> + >>> + /* >>> + * Compared with the previous SoCs, self-adaption current module >>> + * is newly added for A1, keep the new power-on sequence to enable the >>> + * PLL. The sequence is: >>> + * 1. enable the pll, delay for 10us >>> + * 2. enable the pll self-adaption current module, delay for 40us >>> + * 3. enable the lock detect module >>> + */ >>> + if (MESON_PARM_APPLICABLE(&pll->current_en)) { >>> + udelay(10); >>> + meson_parm_write(clk->map, &pll->current_en, 1); >>> + udelay(40); >>> + }; >>> + >>> + if (MESON_PARM_APPLICABLE(&pll->l_detect)) { >>> + meson_parm_write(clk->map, &pll->l_detect, 1); >>> + meson_parm_write(clk->map, &pll->l_detect, 0); >>> + } >>> if (meson_clk_pll_wait_lock(hw)) >>> return -EIO; >>> @@ -343,10 +371,15 @@ static void meson_clk_pll_disable(struct clk_hw *hw) >>> struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); >>> /* Put the pll is in reset */ >>> - meson_parm_write(clk->map, &pll->rst, 1); >>> + if (MESON_PARM_APPLICABLE(&pll->rst)) >>> + meson_parm_write(clk->map, &pll->rst, 1); >>> /* Disable the pll */ >>> meson_parm_write(clk->map, &pll->en, 0); >>> + >>> + /* Disable PLL internal self-adaption current module */ >>> + if (MESON_PARM_APPLICABLE(&pll->current_en)) >>> + meson_parm_write(clk->map, &pll->current_en, 0); >>> } >> >> With the above clarified, it should be easy to properly split the >> functions between the legacy type and the a1 type. >> >> You'll need to update meson_clk_pll_set_rate() to call >> - clk_hw_is_enabled() >> - clk_hw_enable() and clk_hw_disable() (again, you'll need to add >> those in the framework first) >> >>> static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long >>> rate, >>> diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h >>> index 367efd0f6410..a2228c0fdce5 100644 >>> --- a/drivers/clk/meson/clk-pll.h >>> +++ b/drivers/clk/meson/clk-pll.h >>> @@ -36,6 +36,8 @@ struct meson_clk_pll_data { >>> struct parm frac; >>> struct parm l; >>> struct parm rst; >>> + struct parm current_en; >>> + struct parm l_detect; >>> const struct reg_sequence *init_regs; >>> unsigned int init_count; >>> const struct pll_params_table *table; >> >> . >>
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c index ddb1e5634739..10926291440f 100644 --- a/drivers/clk/meson/clk-pll.c +++ b/drivers/clk/meson/clk-pll.c @@ -283,10 +283,14 @@ static void meson_clk_pll_init(struct clk_hw *hw) struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); if (pll->init_count) { - meson_parm_write(clk->map, &pll->rst, 1); + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 1); + regmap_multi_reg_write(clk->map, pll->init_regs, pll->init_count); - meson_parm_write(clk->map, &pll->rst, 0); + + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 0); } } @@ -295,8 +299,11 @@ static int meson_clk_pll_is_enabled(struct clk_hw *hw) struct clk_regmap *clk = to_clk_regmap(hw); struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); - if (meson_parm_read(clk->map, &pll->rst) || - !meson_parm_read(clk->map, &pll->en) || + if (MESON_PARM_APPLICABLE(&pll->rst) && + meson_parm_read(clk->map, &pll->rst)) + return 0; + + if (!meson_parm_read(clk->map, &pll->en) || !meson_parm_read(clk->map, &pll->l)) return 0; @@ -323,13 +330,34 @@ static int meson_clk_pll_enable(struct clk_hw *hw) return 0; /* Make sure the pll is in reset */ - meson_parm_write(clk->map, &pll->rst, 1); + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 1); /* Enable the pll */ meson_parm_write(clk->map, &pll->en, 1); /* Take the pll out reset */ - meson_parm_write(clk->map, &pll->rst, 0); + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 0); + + /* + * Compared with the previous SoCs, self-adaption current module + * is newly added for A1, keep the new power-on sequence to enable the + * PLL. The sequence is: + * 1. enable the pll, delay for 10us + * 2. enable the pll self-adaption current module, delay for 40us + * 3. enable the lock detect module + */ + if (MESON_PARM_APPLICABLE(&pll->current_en)) { + udelay(10); + meson_parm_write(clk->map, &pll->current_en, 1); + udelay(40); + }; + + if (MESON_PARM_APPLICABLE(&pll->l_detect)) { + meson_parm_write(clk->map, &pll->l_detect, 1); + meson_parm_write(clk->map, &pll->l_detect, 0); + } if (meson_clk_pll_wait_lock(hw)) return -EIO; @@ -343,10 +371,15 @@ static void meson_clk_pll_disable(struct clk_hw *hw) struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); /* Put the pll is in reset */ - meson_parm_write(clk->map, &pll->rst, 1); + if (MESON_PARM_APPLICABLE(&pll->rst)) + meson_parm_write(clk->map, &pll->rst, 1); /* Disable the pll */ meson_parm_write(clk->map, &pll->en, 0); + + /* Disable PLL internal self-adaption current module */ + if (MESON_PARM_APPLICABLE(&pll->current_en)) + meson_parm_write(clk->map, &pll->current_en, 0); } static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h index 367efd0f6410..a2228c0fdce5 100644 --- a/drivers/clk/meson/clk-pll.h +++ b/drivers/clk/meson/clk-pll.h @@ -36,6 +36,8 @@ struct meson_clk_pll_data { struct parm frac; struct parm l; struct parm rst; + struct parm current_en; + struct parm l_detect; const struct reg_sequence *init_regs; unsigned int init_count; const struct pll_params_table *table;