| Message ID | 20200210095600.77894-1-maxime@cerno.tech (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 4ae7a3c3d7d31260f690d8d658f0365f3eca67a2 |
| Headers | show |
| Series | [1/2] arm64: dts: allwinner: h5: Fix PMU compatible | expand |
On Mon, 10 Feb 2020 10:55:59 +0100 Maxime Ripard <maxime@cerno.tech> wrote: Hi, > The commit c35a516a4618 ("arm64: dts: allwinner: H5: Add PMU node") > introduced support for the PMU found on the Allwinner H5. However, the > binding only allows for a single compatible, while the patch was adding > two. Maxime, thanks for bringing this up, was that found by some validation tool? And while this is true, I wonder if this was intentional? I see several other combinations of PMU compatibles in the tree. Mark, Rob, can you shed any light on this? Actually I am wondering why we would need the PMU type in the first place, isn't that discoverable via the MIDR? And all we actually need from the DT is the interrupts and maybe some quirk info? It looks like ACPI is always using the generic PMUv3 map, so wouldn't it actually be better to replace the compatible string matching with MIDR matching? Or are those core specific maps somewhat obsolete anyway? Since I don't see any newer cores in there? Cheers, Andre > Make sure we follow the binding. > > Fixes: c35a516a4618 ("arm64: dts: allwinner: H5: Add PMU node") > Signed-off-by: Maxime Ripard <maxime@cerno.tech> > --- > arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi > index 9893aa64dd0b..4462a68c0681 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi > @@ -38,8 +38,7 @@ cpu3: cpu@3 { > }; > > pmu { > - compatible = "arm,cortex-a53-pmu", > - "arm,armv8-pmuv3"; > + compatible = "arm,cortex-a53-pmu"; > interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, > <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
On 14/02/2020 6:04 pm, Andre Przywara wrote: > On Mon, 10 Feb 2020 10:55:59 +0100 > Maxime Ripard <maxime@cerno.tech> wrote: > > Hi, > >> The commit c35a516a4618 ("arm64: dts: allwinner: H5: Add PMU node") >> introduced support for the PMU found on the Allwinner H5. However, the >> binding only allows for a single compatible, while the patch was adding >> two. > > Maxime, thanks for bringing this up, was that found by some validation tool? > > And while this is true, I wonder if this was intentional? > I see several other combinations of PMU compatibles in the tree. > > Mark, Rob, can you shed any light on this? > > Actually I am wondering why we would need the PMU type in the first place, isn't that discoverable via the MIDR? "the" MIDR... ;) Usual big.LITTLE vs. CPU hotplug rules apply. > And all we actually need from the DT is the interrupts and maybe some quirk info? > > It looks like ACPI is always using the generic PMUv3 map, so wouldn't it actually be better to replace the compatible string matching with MIDR matching? Or are those core specific maps somewhat obsolete anyway? Since I don't see any newer cores in there? Mostly they're just long overdue for an update (and somewhat mitigated by the userspace JSON stuff in perf tools, but in principle there are still other users of perf_events). IIRC, the generic PMUv3 compatible was only ever meant to be for things like the AEM without a specific microarchitecture (cf. the "arm,armv8" CPU binding). Robin. > > Cheers, > Andre > >> Make sure we follow the binding. > > >> >> Fixes: c35a516a4618 ("arm64: dts: allwinner: H5: Add PMU node") >> Signed-off-by: Maxime Ripard <maxime@cerno.tech> >> --- >> arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +-- >> 1 file changed, 1 insertion(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi >> index 9893aa64dd0b..4462a68c0681 100644 >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi >> @@ -38,8 +38,7 @@ cpu3: cpu@3 { >> }; >> >> pmu { >> - compatible = "arm,cortex-a53-pmu", >> - "arm,armv8-pmuv3"; >> + compatible = "arm,cortex-a53-pmu"; >> interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, >> <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, >> <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >
Hi Andre, On Fri, Feb 14, 2020 at 06:04:04PM +0000, Andre Przywara wrote: > > The commit c35a516a4618 ("arm64: dts: allwinner: H5: Add PMU node") > > introduced support for the PMU found on the Allwinner H5. However, the > > binding only allows for a single compatible, while the patch was adding > > two. > > Maxime, thanks for bringing this up, was that found by some > validation tool? Indeed. > And while this is true, I wonder if this was intentional? Either the YAML file: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/pmu.yaml Or the text file that was there before it: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/pmu.txt?id=v5.0 Make it pretty clear that only a single entry is expected > I see several other combinations of PMU compatibles in the tree. I've probably sent around 50-100 patches for DT not following the binding on Allwinner platforms alone, so it doesn't really surprise me :) Maxime
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi index 9893aa64dd0b..4462a68c0681 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi @@ -38,8 +38,7 @@ cpu3: cpu@3 { }; pmu { - compatible = "arm,cortex-a53-pmu", - "arm,armv8-pmuv3"; + compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
The commit c35a516a4618 ("arm64: dts: allwinner: H5: Add PMU node") introduced support for the PMU found on the Allwinner H5. However, the binding only allows for a single compatible, while the patch was adding two. Make sure we follow the binding. Fixes: c35a516a4618 ("arm64: dts: allwinner: H5: Add PMU node") Signed-off-by: Maxime Ripard <maxime@cerno.tech> --- arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)