| Message ID | 20200216185324.32596-2-maz@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Random debug/PMU fixes for 5.6 | expand |
Hi Marc, $subject typo: ~/DBGBIDR/DBGDIDR/ On 16/02/2020 18:53, Marc Zyngier wrote: > The AArch32 CP14 DBGDIDR has bit 15 set to RES1, which our current > emulation doesn't set. Just add the missing bit. So it does. Reviewed-by: James Morse <james.morse@arm.com> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 3e909b117f0c..da82c4b03aab 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1658,7 +1658,7 @@ static bool trap_dbgidr(struct kvm_vcpu *vcpu, > p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | > (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | > (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) > - | (6 << 16) | (el3 << 14) | (el3 << 12)); > + | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); Hmmm, where el3 is: | u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); Aren't we depending on the compilers 'true' being 1 here? Thanks, James
On 18/02/2020 5:43 pm, James Morse wrote: > Hi Marc, > > $subject typo: ~/DBGBIDR/DBGDIDR/ > > On 16/02/2020 18:53, Marc Zyngier wrote: >> The AArch32 CP14 DBGDIDR has bit 15 set to RES1, which our current >> emulation doesn't set. Just add the missing bit. > > So it does. > > Reviewed-by: James Morse <james.morse@arm.com> > > >> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >> index 3e909b117f0c..da82c4b03aab 100644 >> --- a/arch/arm64/kvm/sys_regs.c >> +++ b/arch/arm64/kvm/sys_regs.c >> @@ -1658,7 +1658,7 @@ static bool trap_dbgidr(struct kvm_vcpu *vcpu, >> p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | >> (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | >> (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) >> - | (6 << 16) | (el3 << 14) | (el3 << 12)); >> + | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); > > Hmmm, where el3 is: > | u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); > > Aren't we depending on the compilers 'true' being 1 here? Pretty much, but thankfully the only compilers we support are C compilers: "The result of the logical negation operator ! is 0 if the value of its operand compares unequal to 0, 1 if the value of its operand compares equal to 0. The result has type int." And now I have you to thank for flashbacks to bitwise logical operators in Visual Basic... :P Robin.
Hi Robin, On 18/02/2020 18:01, Robin Murphy wrote: > On 18/02/2020 5:43 pm, James Morse wrote: >> On 16/02/2020 18:53, Marc Zyngier wrote: >>> The AArch32 CP14 DBGDIDR has bit 15 set to RES1, which our current >>> emulation doesn't set. Just add the missing bit. >>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >>> index 3e909b117f0c..da82c4b03aab 100644 >>> --- a/arch/arm64/kvm/sys_regs.c >>> +++ b/arch/arm64/kvm/sys_regs.c >>> @@ -1658,7 +1658,7 @@ static bool trap_dbgidr(struct kvm_vcpu *vcpu, >>> p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | >>> (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | >>> (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) >>> - | (6 << 16) | (el3 << 14) | (el3 << 12)); >>> + | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); >> >> Hmmm, where el3 is: >> | u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT); >> >> Aren't we depending on the compilers 'true' being 1 here? > > Pretty much, but thankfully the only compilers we support are C compilers: > > "The result of the logical negation operator ! is 0 if the value of its operand compares > unequal to 0, 1 if the value of its operand compares equal to 0. The result has type int." Excellent. I thought this was the sort of thing that couldn't be depended on! > And now I have you to thank for flashbacks to bitwise logical operators in Visual Basic... :P ... sorry? Thanks, James
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 3e909b117f0c..da82c4b03aab 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1658,7 +1658,7 @@ static bool trap_dbgidr(struct kvm_vcpu *vcpu, p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | (((dfr >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) << 20) - | (6 << 16) | (el3 << 14) | (el3 << 12)); + | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12)); return true; } }
The AArch32 CP14 DBGDIDR has bit 15 set to RES1, which our current emulation doesn't set. Just add the missing bit. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> --- arch/arm64/kvm/sys_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)