| Message ID | 20200220195845.5676-1-andrew.cooper3@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | x86/splitlock: CPUID and MSR details | expand |
On Thu, Feb 20, 2020 at 07:58:45PM +0000, Andrew Cooper wrote: > A splitlock is an atomic operation which crosses a cache line boundary. It > serialises operations in the cache coherency fabric and comes with a > multi-thousand cycle stall. > > Intel Tremont CPUs introduce MSR_CORE_CAPS to enumerate various core-specific > features, and MSR_TEST_CTRL to adjust the behaviour in the case of a > splitlock. > > Virtualising this for guests is distinctly tricky owing to the fact that > MSR_TEST_CTRL has core rather than thread scope. In the meantime however, > prevent the MSR values leaking into guests. > > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Reviewed-by: Wei Liu <wl@xen.org>
On 20.02.2020 20:58, Andrew Cooper wrote: > A splitlock is an atomic operation which crosses a cache line boundary. It > serialises operations in the cache coherency fabric and comes with a > multi-thousand cycle stall. > > Intel Tremont CPUs introduce MSR_CORE_CAPS to enumerate various core-specific > features, and MSR_TEST_CTRL to adjust the behaviour in the case of a > splitlock. > > Virtualising this for guests is distinctly tricky owing to the fact that > MSR_TEST_CTRL has core rather than thread scope. In the meantime however, > prevent the MSR values leaking into guests. > > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Feel free to throw in - with Wei's R-b you don't need my ack anymore, but I thought I'd reply anyway to avoid you having to wait a couple of days. Jan
diff --git a/tools/libxl/libxl_cpuid.c b/tools/libxl/libxl_cpuid.c index 062750102e..b4f6fd590d 100644 --- a/tools/libxl/libxl_cpuid.c +++ b/tools/libxl/libxl_cpuid.c @@ -217,6 +217,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str) {"stibp", 0x00000007, 0, CPUID_REG_EDX, 27, 1}, {"l1d-flush", 0x00000007, 0, CPUID_REG_EDX, 28, 1}, {"arch-caps", 0x00000007, 0, CPUID_REG_EDX, 29, 1}, + {"core-caps", 0x00000007, 0, CPUID_REG_EDX, 30, 1}, {"ssbd", 0x00000007, 0, CPUID_REG_EDX, 31, 1}, {"avx512-bf16", 0x00000007, 1, CPUID_REG_EAX, 5, 1}, diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index 8be03d81ce..7726c4ed3c 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -166,7 +166,7 @@ static const char *const str_7d0[32] = [26] = "ibrsb", [27] = "stibp", [28] = "l1d_flush", [29] = "arch_caps", - /* 30 */ [31] = "ssbd", + [30] = "core_caps", [31] = "ssbd", }; static const char *const str_7a1[32] = diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index 1cea777680..dd26c87758 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -132,6 +132,8 @@ int guest_rdmsr(struct vcpu *v, uint32_t msr, uint64_t *val) case MSR_PRED_CMD: case MSR_FLUSH_CMD: /* Write-only */ + case MSR_TEST_CTRL: + case MSR_CORE_CAPABILITIES: case MSR_TSX_FORCE_ABORT: case MSR_TSX_CTRL: case MSR_AMD64_LWP_CFG: @@ -283,10 +285,12 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) uint64_t rsvd; case MSR_IA32_PLATFORM_ID: + case MSR_CORE_CAPABILITIES: case MSR_INTEL_CORE_THREAD_COUNT: case MSR_INTEL_PLATFORM_INFO: case MSR_ARCH_CAPABILITIES: /* Read-only */ + case MSR_TEST_CTRL: case MSR_TSX_FORCE_ABORT: case MSR_TSX_CTRL: case MSR_AMD64_LWP_CFG: diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h index bbca3289ca..c320846c06 100644 --- a/xen/include/asm-x86/msr-index.h +++ b/xen/include/asm-x86/msr-index.h @@ -32,6 +32,10 @@ #define EFER_KNOWN_MASK (EFER_SCE | EFER_LME | EFER_LMA | EFER_NX | \ EFER_SVME | EFER_FFXSE) +#define MSR_TEST_CTRL 0x00000033 +#define TEST_CTRL_SPLITLOCK_DETECT (_AC(1, ULL) << 29) +#define TEST_CTRL_SPLITLOCK_DISABLE (_AC(1, ULL) << 31) + #define MSR_INTEL_CORE_THREAD_COUNT 0x00000035 #define MSR_CTC_THREAD_MASK 0x0000ffff #define MSR_CTC_CORE_MASK 0xffff0000 @@ -52,6 +56,9 @@ #define PPIN_LOCKOUT (_AC(1, ULL) << 0) #define PPIN_ENABLE (_AC(1, ULL) << 1) +#define MSR_CORE_CAPABILITIES 0x000000cf +#define CORE_CAPS_SPLITLOCK_DETECT (_AC(1, ULL) << 5) + #define MSR_ARCH_CAPABILITIES 0x0000010a #define ARCH_CAPS_RDCL_NO (_AC(1, ULL) << 0) #define ARCH_CAPS_IBRS_ALL (_AC(1, ULL) << 1) diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index bd2f21cb85..086736ac7b 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -258,6 +258,7 @@ XEN_CPUFEATURE(IBRSB, 9*32+26) /*A IBRS and IBPB support (used by Intel XEN_CPUFEATURE(STIBP, 9*32+27) /*A STIBP */ XEN_CPUFEATURE(L1D_FLUSH, 9*32+28) /*S MSR_FLUSH_CMD and L1D flush. */ XEN_CPUFEATURE(ARCH_CAPS, 9*32+29) /* IA32_ARCH_CAPABILITIES MSR */ +XEN_CPUFEATURE(CORE_CAPS, 9*32+30) /* IA32_CORE_CAPABILITIES MSR */ XEN_CPUFEATURE(SSBD, 9*32+31) /*A MSR_SPEC_CTRL.SSBD available */ /* Intel-defined CPU features, CPUID level 0x00000007:1.eax, word 10 */
A splitlock is an atomic operation which crosses a cache line boundary. It serialises operations in the cache coherency fabric and comes with a multi-thousand cycle stall. Intel Tremont CPUs introduce MSR_CORE_CAPS to enumerate various core-specific features, and MSR_TEST_CTRL to adjust the behaviour in the case of a splitlock. Virtualising this for guests is distinctly tricky owing to the fact that MSR_TEST_CTRL has core rather than thread scope. In the meantime however, prevent the MSR values leaking into guests. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> --- CC: Jan Beulich <JBeulich@suse.com> CC: Wei Liu <wl@xen.org> CC: Roger Pau Monné <roger.pau@citrix.com> --- tools/libxl/libxl_cpuid.c | 1 + tools/misc/xen-cpuid.c | 2 +- xen/arch/x86/msr.c | 4 ++++ xen/include/asm-x86/msr-index.h | 7 +++++++ xen/include/public/arch-x86/cpufeatureset.h | 1 + 5 files changed, 14 insertions(+), 1 deletion(-)