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Wed, 19 Feb 2020 10:23:08 +0000 From: peng.fan@nxp.com To: sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, abel.vesa@nxp.com, leonard.crestez@nxp.com Cc: kernel@pengutronix.de, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, anson.huang@nxp.com, ping.bai@nxp.com, l.stach@pengutronix.de, Peng Fan <peng.fan@nxp.com> Subject: [PATCH RESEND v3 0/4] clk: imx: imx8m: fix a53 cpu clock Date: Wed, 19 Feb 2020 18:17:05 +0800 Message-Id: <1582107429-21123-1-git-send-email-peng.fan@nxp.com> X-Mailer: git-send-email 2.7.4 Content-Type: text/plain X-ClientProxiedBy: HKAPR04CA0014.apcprd04.prod.outlook.com (2603:1096:203:d0::24) To AM0PR04MB4481.eurprd04.prod.outlook.com (2603:10a6:208:70::15) MIME-Version: 1.0 Received: from localhost.localdomain (119.31.174.66) by HKAPR04CA0014.apcprd04.prod.outlook.com (2603:1096:203:d0::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.2729.23 via Frontend Transport; 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clk: imx: imx8m: fix a53 cpu clock
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On Wed, Feb 19, 2020 at 06:17:05PM +0800, peng.fan@nxp.com wrote: > From: Peng Fan <peng.fan@nxp.com> > > V3: > Rebased to Shawn's for-next branch > Typo fix > > V2: > Fix i.MX8MP build > Update cover letter, i.MX7D not have this issue > > The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root > signoff timing is 1Ghz, however the A53 core which sources from CCM > root could run above 1GHz which voilates the CCM. > > There is a CORE_SEL slice before A53 core, we need configure the > CORE_SEL slice source from ARM PLL, not A53 CCM clk root. > > The A53 CCM clk root should only be used when need to change ARM PLL > frequency. > > Peng Fan (4): > clk: imx: imx8mq: fix a53 cpu clock > clk: imx: imx8mm: fix a53 cpu clock > clk: imx: imx8mn: fix a53 cpu clock > clk: imx: imx8mp: fix a53 cpu clock Applied all, thanks.
From: Peng Fan <peng.fan@nxp.com> V3: Rebased to Shawn's for-next branch Typo fix V2: Fix i.MX8MP build Update cover letter, i.MX7D not have this issue The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root signoff timing is 1Ghz, however the A53 core which sources from CCM root could run above 1GHz which voilates the CCM. There is a CORE_SEL slice before A53 core, we need configure the CORE_SEL slice source from ARM PLL, not A53 CCM clk root. The A53 CCM clk root should only be used when need to change ARM PLL frequency. Peng Fan (4): clk: imx: imx8mq: fix a53 cpu clock clk: imx: imx8mm: fix a53 cpu clock clk: imx: imx8mn: fix a53 cpu clock clk: imx: imx8mp: fix a53 cpu clock drivers/clk/imx/clk-imx8mm.c | 16 ++++++++++++---- drivers/clk/imx/clk-imx8mn.c | 16 ++++++++++++---- drivers/clk/imx/clk-imx8mp.c | 16 ++++++++++++---- drivers/clk/imx/clk-imx8mq.c | 16 ++++++++++++---- include/dt-bindings/clock/imx8mm-clock.h | 4 +++- include/dt-bindings/clock/imx8mn-clock.h | 4 +++- include/dt-bindings/clock/imx8mp-clock.h | 3 ++- include/dt-bindings/clock/imx8mq-clock.h | 4 +++- 8 files changed, 59 insertions(+), 20 deletions(-)