| Message ID | 20200225094057.120144-2-jitao.shi@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mt8183 dpi supports dual edge and pin mode swap | expand |
On Tue, 2020-02-25 at 17:40 +0800, Jitao Shi wrote: > Some chips's sample mode are rising, falling and dual edge (both > falling and rising edge). > Extern the pclk-sample property to support dual edge. > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > --- > Documentation/devicetree/bindings/media/video-interfaces.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt > index f884ada0bffc..da9ad24935db 100644 > --- a/Documentation/devicetree/bindings/media/video-interfaces.txt > +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt > @@ -118,8 +118,8 @@ Optional endpoint properties > - data-enable-active: similar to HSYNC and VSYNC, specifies the data enable > signal polarity. > - field-even-active: field signal level during the even field data transmission. > -- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock > - signal. > +- pclk-sample: sample data on rising (1), falling (0) or both rising and > + falling (2) edge of the pixel clock signal. > - sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for > LOW/HIGH respectively. > - data-lanes: an array of physical data lane indexes. Position of an entry
diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt index f884ada0bffc..da9ad24935db 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.txt +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt @@ -118,8 +118,8 @@ Optional endpoint properties - data-enable-active: similar to HSYNC and VSYNC, specifies the data enable signal polarity. - field-even-active: field signal level during the even field data transmission. -- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock - signal. +- pclk-sample: sample data on rising (1), falling (0) or both rising and + falling (2) edge of the pixel clock signal. - sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively. - data-lanes: an array of physical data lane indexes. Position of an entry
Some chips's sample mode are rising, falling and dual edge (both falling and rising edge). Extern the pclk-sample property to support dual edge. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> --- Documentation/devicetree/bindings/media/video-interfaces.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)