diff mbox series

[v2,01/20] drm/i915: Handle some leftover s/intel_crtc/crtc/

Message ID 20200225171125.28885-2-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: Proper dbuf global state | expand

Commit Message

Ville Syrjälä Feb. 25, 2020, 5:11 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Switch to the preferred 'crtc' name for our crtc variables.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

Comments

Jani Nikula Feb. 26, 2020, 9:29 a.m. UTC | #1 
On Tue, 25 Feb 2020, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Switch to the preferred 'crtc' name for our crtc variables.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 23 +++++++++++------------
>  1 file changed, 11 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 22aa205793e5..543634d3e10c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2776,7 +2776,7 @@ static bool ilk_validate_wm_level(int level,
>  }
>  
>  static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
> -				 const struct intel_crtc *intel_crtc,
> +				 const struct intel_crtc *crtc,
>  				 int level,
>  				 struct intel_crtc_state *crtc_state,
>  				 const struct intel_plane_state *pristate,
> @@ -3107,7 +3107,7 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
>  static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_pipe_wm *pipe_wm;
>  	struct intel_plane *plane;
>  	const struct intel_plane_state *plane_state;
> @@ -3147,7 +3147,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>  		usable_level = 0;
>  
>  	memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
> -	ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
> +	ilk_compute_wm_level(dev_priv, crtc, 0, crtc_state,
>  			     pristate, sprstate, curstate, &pipe_wm->wm[0]);
>  
>  	if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
> @@ -3158,7 +3158,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
>  	for (level = 1; level <= usable_level; level++) {
>  		struct intel_wm_level *wm = &pipe_wm->wm[level];
>  
> -		ilk_compute_wm_level(dev_priv, intel_crtc, level, crtc_state,
> +		ilk_compute_wm_level(dev_priv, crtc, level, crtc_state,
>  				     pristate, sprstate, curstate, wm);
>  
>  		/*
> @@ -4549,9 +4549,8 @@ static int
>  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_atomic_state *state = crtc_state->uapi.state;
> -	struct drm_crtc *crtc = crtc_state->uapi.crtc;
> -	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
>  	u16 alloc_size, start = 0;
>  	u16 total[I915_MAX_PLANES] = {};
> @@ -4609,7 +4608,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>  	 */
>  	for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
>  		blocks = 0;
> -		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +		for_each_plane_id_on_crtc(crtc, plane_id) {
>  			const struct skl_plane_wm *wm =
>  				&crtc_state->wm.skl.optimal.planes[plane_id];
>  
> @@ -4646,7 +4645,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>  	 * watermark level, plus an extra share of the leftover blocks
>  	 * proportional to its relative data rate.
>  	 */
> -	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +	for_each_plane_id_on_crtc(crtc, plane_id) {
>  		const struct skl_plane_wm *wm =
>  			&crtc_state->wm.skl.optimal.planes[plane_id];
>  		u64 rate;
> @@ -4685,7 +4684,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>  
>  	/* Set the actual DDB start/end points for each plane */
>  	start = alloc->start;
> -	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +	for_each_plane_id_on_crtc(crtc, plane_id) {
>  		struct skl_ddb_entry *plane_alloc =
>  			&crtc_state->wm.skl.plane_ddb_y[plane_id];
>  		struct skl_ddb_entry *uv_plane_alloc =
> @@ -4719,7 +4718,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>  	 * that aren't actually possible.
>  	 */
>  	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> -		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +		for_each_plane_id_on_crtc(crtc, plane_id) {
>  			struct skl_plane_wm *wm =
>  				&crtc_state->wm.skl.optimal.planes[plane_id];
>  
> @@ -4756,7 +4755,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
>  	 * Go back and disable the transition watermark if it turns out we
>  	 * don't have enough DDB blocks for it.
>  	 */
> -	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +	for_each_plane_id_on_crtc(crtc, plane_id) {
>  		struct skl_plane_wm *wm =
>  			&crtc_state->wm.skl.optimal.planes[plane_id];
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 22aa205793e5..543634d3e10c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2776,7 +2776,7 @@  static bool ilk_validate_wm_level(int level,
 }
 
 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
-				 const struct intel_crtc *intel_crtc,
+				 const struct intel_crtc *crtc,
 				 int level,
 				 struct intel_crtc_state *crtc_state,
 				 const struct intel_plane_state *pristate,
@@ -3107,7 +3107,7 @@  static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
 static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_pipe_wm *pipe_wm;
 	struct intel_plane *plane;
 	const struct intel_plane_state *plane_state;
@@ -3147,7 +3147,7 @@  static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 		usable_level = 0;
 
 	memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
-	ilk_compute_wm_level(dev_priv, intel_crtc, 0, crtc_state,
+	ilk_compute_wm_level(dev_priv, crtc, 0, crtc_state,
 			     pristate, sprstate, curstate, &pipe_wm->wm[0]);
 
 	if (!ilk_validate_pipe_wm(dev_priv, pipe_wm))
@@ -3158,7 +3158,7 @@  static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
 	for (level = 1; level <= usable_level; level++) {
 		struct intel_wm_level *wm = &pipe_wm->wm[level];
 
-		ilk_compute_wm_level(dev_priv, intel_crtc, level, crtc_state,
+		ilk_compute_wm_level(dev_priv, crtc, level, crtc_state,
 				     pristate, sprstate, curstate, wm);
 
 		/*
@@ -4549,9 +4549,8 @@  static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 {
 	struct drm_atomic_state *state = crtc_state->uapi.state;
-	struct drm_crtc *crtc = crtc_state->uapi.crtc;
-	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
 	u16 alloc_size, start = 0;
 	u16 total[I915_MAX_PLANES] = {};
@@ -4609,7 +4608,7 @@  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	 */
 	for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
 		blocks = 0;
-		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		for_each_plane_id_on_crtc(crtc, plane_id) {
 			const struct skl_plane_wm *wm =
 				&crtc_state->wm.skl.optimal.planes[plane_id];
 
@@ -4646,7 +4645,7 @@  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	 * watermark level, plus an extra share of the leftover blocks
 	 * proportional to its relative data rate.
 	 */
-	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+	for_each_plane_id_on_crtc(crtc, plane_id) {
 		const struct skl_plane_wm *wm =
 			&crtc_state->wm.skl.optimal.planes[plane_id];
 		u64 rate;
@@ -4685,7 +4684,7 @@  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 
 	/* Set the actual DDB start/end points for each plane */
 	start = alloc->start;
-	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+	for_each_plane_id_on_crtc(crtc, plane_id) {
 		struct skl_ddb_entry *plane_alloc =
 			&crtc_state->wm.skl.plane_ddb_y[plane_id];
 		struct skl_ddb_entry *uv_plane_alloc =
@@ -4719,7 +4718,7 @@  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	 * that aren't actually possible.
 	 */
 	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
-		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		for_each_plane_id_on_crtc(crtc, plane_id) {
 			struct skl_plane_wm *wm =
 				&crtc_state->wm.skl.optimal.planes[plane_id];
 
@@ -4756,7 +4755,7 @@  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
 	 * Go back and disable the transition watermark if it turns out we
 	 * don't have enough DDB blocks for it.
 	 */
-	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+	for_each_plane_id_on_crtc(crtc, plane_id) {
 		struct skl_plane_wm *wm =
 			&crtc_state->wm.skl.optimal.planes[plane_id];