| Message ID | 20200225171125.28885-5-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Proper dbuf global state | expand |
On Tue, 25 Feb 2020, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Make life a bit simpler by sticking a sentinel at the end of > the dbuf slice arrays. This way we don't need to pass in the > size. Also unify the types (u8 vs. u32) for active_pipes. > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 34 +++++++++++++-------------------- > 1 file changed, 13 insertions(+), 21 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index abeb4b19071f..a2e78969c0df 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3843,7 +3843,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv) > } > > static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state, > - u32 active_pipes); > + u8 active_pipes); > > static void > skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, > @@ -4228,6 +4228,7 @@ static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] = > [PIPE_C] = BIT(DBUF_S2), > }, > }, > + {} > }; > > /* > @@ -4350,16 +4351,15 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = > [PIPE_D] = BIT(DBUF_S2), > }, > }, > + {} > }; > > -static u8 compute_dbuf_slices(enum pipe pipe, > - u32 active_pipes, > - const struct dbuf_slice_conf_entry *dbuf_slices, > - int size) > +static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, > + const struct dbuf_slice_conf_entry *dbuf_slices) > { > int i; > > - for (i = 0; i < size; i++) { > + for (i = 0; i < dbuf_slices[i].active_pipes; i++) { > if (dbuf_slices[i].active_pipes == active_pipes) > return dbuf_slices[i].dbuf_mask[pipe]; > } > @@ -4371,8 +4371,7 @@ static u8 compute_dbuf_slices(enum pipe pipe, > * returns correspondent DBuf slice mask as stated in BSpec for particular > * platform. > */ > -static u32 icl_compute_dbuf_slices(enum pipe pipe, > - u32 active_pipes) > +static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes) > { > /* > * FIXME: For ICL this is still a bit unclear as prev BSpec revision > @@ -4386,32 +4385,25 @@ static u32 icl_compute_dbuf_slices(enum pipe pipe, > * still here - we will need it once those additional constraints > * pop up. > */ > - return compute_dbuf_slices(pipe, active_pipes, > - icl_allowed_dbufs, > - ARRAY_SIZE(icl_allowed_dbufs)); > + return compute_dbuf_slices(pipe, active_pipes, icl_allowed_dbufs); > } > > -static u32 tgl_compute_dbuf_slices(enum pipe pipe, > - u32 active_pipes) > +static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes) > { > - return compute_dbuf_slices(pipe, active_pipes, > - tgl_allowed_dbufs, > - ARRAY_SIZE(tgl_allowed_dbufs)); > + return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs); > } > > static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state, > - u32 active_pipes) > + u8 active_pipes) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); > enum pipe pipe = crtc->pipe; > > if (IS_GEN(dev_priv, 12)) > - return tgl_compute_dbuf_slices(pipe, > - active_pipes); > + return tgl_compute_dbuf_slices(pipe, active_pipes); > else if (IS_GEN(dev_priv, 11)) > - return icl_compute_dbuf_slices(pipe, > - active_pipes); > + return icl_compute_dbuf_slices(pipe, active_pipes); > /* > * For anything else just return one slice yet. > * Should be extended for other platforms.
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index abeb4b19071f..a2e78969c0df 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3843,7 +3843,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv) } static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state, - u32 active_pipes); + u8 active_pipes); static void skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv, @@ -4228,6 +4228,7 @@ static const struct dbuf_slice_conf_entry icl_allowed_dbufs[] = [PIPE_C] = BIT(DBUF_S2), }, }, + {} }; /* @@ -4350,16 +4351,15 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = [PIPE_D] = BIT(DBUF_S2), }, }, + {} }; -static u8 compute_dbuf_slices(enum pipe pipe, - u32 active_pipes, - const struct dbuf_slice_conf_entry *dbuf_slices, - int size) +static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes, + const struct dbuf_slice_conf_entry *dbuf_slices) { int i; - for (i = 0; i < size; i++) { + for (i = 0; i < dbuf_slices[i].active_pipes; i++) { if (dbuf_slices[i].active_pipes == active_pipes) return dbuf_slices[i].dbuf_mask[pipe]; } @@ -4371,8 +4371,7 @@ static u8 compute_dbuf_slices(enum pipe pipe, * returns correspondent DBuf slice mask as stated in BSpec for particular * platform. */ -static u32 icl_compute_dbuf_slices(enum pipe pipe, - u32 active_pipes) +static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes) { /* * FIXME: For ICL this is still a bit unclear as prev BSpec revision @@ -4386,32 +4385,25 @@ static u32 icl_compute_dbuf_slices(enum pipe pipe, * still here - we will need it once those additional constraints * pop up. */ - return compute_dbuf_slices(pipe, active_pipes, - icl_allowed_dbufs, - ARRAY_SIZE(icl_allowed_dbufs)); + return compute_dbuf_slices(pipe, active_pipes, icl_allowed_dbufs); } -static u32 tgl_compute_dbuf_slices(enum pipe pipe, - u32 active_pipes) +static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes) { - return compute_dbuf_slices(pipe, active_pipes, - tgl_allowed_dbufs, - ARRAY_SIZE(tgl_allowed_dbufs)); + return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs); } static u8 skl_compute_dbuf_slices(const struct intel_crtc_state *crtc_state, - u32 active_pipes) + u8 active_pipes) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; if (IS_GEN(dev_priv, 12)) - return tgl_compute_dbuf_slices(pipe, - active_pipes); + return tgl_compute_dbuf_slices(pipe, active_pipes); else if (IS_GEN(dev_priv, 11)) - return icl_compute_dbuf_slices(pipe, - active_pipes); + return icl_compute_dbuf_slices(pipe, active_pipes); /* * For anything else just return one slice yet. * Should be extended for other platforms.