| Message ID | 20200225171125.28885-10-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Proper dbuf global state | expand |
On Tue, 2020-02-25 at 19:11 +0200, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > skl_ddb_get_hw_state() is redundant and kinda called in thw wrong > spot anyway. Just kill it. Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_pm.c | 7 ------- > drivers/gpu/drm/i915/intel_pm.h | 1 - > 2 files changed, 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c > index d4730d9b4e1b..87f88ea6b7ae 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4117,12 +4117,6 @@ void skl_pipe_ddb_get_hw_state(struct > intel_crtc *crtc, > intel_display_power_put(dev_priv, power_domain, wakeref); > } > > -void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv) > -{ > - dev_priv->dbuf.enabled_slices = > - intel_enabled_dbuf_slices_mask(dev_priv); > -} > - > /* > * Determines the downscale amount of a plane for the purposes of > watermark calculations. > * The bspec defines downscale amount as: > @@ -5910,7 +5904,6 @@ void skl_wm_get_hw_state(struct > drm_i915_private *dev_priv) > struct intel_crtc *crtc; > struct intel_crtc_state *crtc_state; > > - skl_ddb_get_hw_state(dev_priv); > for_each_intel_crtc(&dev_priv->drm, crtc) { > crtc_state = to_intel_crtc_state(crtc->base.state); > > diff --git a/drivers/gpu/drm/i915/intel_pm.h > b/drivers/gpu/drm/i915/intel_pm.h > index fadf7cbc44c4..1054a0ab1e40 100644 > --- a/drivers/gpu/drm/i915/intel_pm.h > +++ b/drivers/gpu/drm/i915/intel_pm.h > @@ -38,7 +38,6 @@ u8 intel_enabled_dbuf_slices_mask(struct > drm_i915_private *dev_priv); > void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, > struct skl_ddb_entry *ddb_y, > struct skl_ddb_entry *ddb_uv); > -void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv); > void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, > struct skl_pipe_wm *out); > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index d4730d9b4e1b..87f88ea6b7ae 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4117,12 +4117,6 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, intel_display_power_put(dev_priv, power_domain, wakeref); } -void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv) -{ - dev_priv->dbuf.enabled_slices = - intel_enabled_dbuf_slices_mask(dev_priv); -} - /* * Determines the downscale amount of a plane for the purposes of watermark calculations. * The bspec defines downscale amount as: @@ -5910,7 +5904,6 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv) struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; - skl_ddb_get_hw_state(dev_priv); for_each_intel_crtc(&dev_priv->drm, crtc) { crtc_state = to_intel_crtc_state(crtc->base.state); diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h index fadf7cbc44c4..1054a0ab1e40 100644 --- a/drivers/gpu/drm/i915/intel_pm.h +++ b/drivers/gpu/drm/i915/intel_pm.h @@ -38,7 +38,6 @@ u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *dev_priv); void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc, struct skl_ddb_entry *ddb_y, struct skl_ddb_entry *ddb_uv); -void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv); void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc, struct skl_pipe_wm *out); void g4x_wm_sanitize(struct drm_i915_private *dev_priv);