| Message ID | 1582267156-20189-2-git-send-email-sherry.sun@nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add edac driver for i.MX8MP based on synopsys edac driver | expand |
On Fri, Feb 21, 2020 at 02:39:14PM +0800, sherry sun wrote: > From: Sherry Sun <sherry.sun@nxp.com> > > Add documentation for i.MX8MP DDRC binding based on synopsys_edac doc, > which use the same memory-controller IP. > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com> > --- > .../devicetree/bindings/memory-controllers/synopsys.txt | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > index 9d32762c47e1..5c03959a451f 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > +++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > @@ -6,16 +6,20 @@ bus width configurations. > The Zynq DDR ECC controller has an optional ECC support in half-bus width > (16-bit) configuration. > > -These both ECC controllers correct single bit ECC errors and detect double bit > +The i.MX8MP DDR ECC controller has an ECC support in 64-bit bus width > +configurations. > + > +These all ECC controllers correct single bit ECC errors and detect double bit All the ECC... With that, Reviewed-by: Rob Herring <robh@kernel.org> > ECC errors. > > Required properties: > - compatible: One of: > - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller > - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller > + - 'fsl,imx8mp-ddrc' : i.MX8MP DDR ECC controller > - reg: Should contain DDR controller registers location and length. > > -Required properties for "xlnx,zynqmp-ddrc-2.40a": > +Required properties for "xlnx,zynqmp-ddrc-2.40a" and "fsl,imx8mp-ddrc": > - interrupts: Property with a value describing the interrupt number. > > Example: > -- > 2.17.1 >
Hi Rob, > -----Original Message----- > From: linux-kernel-owner@vger.kernel.org <linux-kernel- > owner@vger.kernel.org> On Behalf Of Rob Herring > Sent: 2020年2月27日 1:25 > To: Sherry Sun <sherry.sun@nxp.com> > Cc: bp@alien8.de; mchehab@kernel.org; tony.luck@intel.com; > james.morse@arm.com; rrichter@marvell.com; michal.simek@xilinx.com; > shawnguo@kernel.org; s.hauer@pengutronix.de; mark.rutland@arm.com; > linux-edac@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; dl-linux-imx > <linux-imx@nxp.com>; Frank Li <frank.li@nxp.com> > Subject: Re: [PATCH 1/3] dt-bindings: memory-controllers: Add i.MX8MP > DDRC binding doc > > On Fri, Feb 21, 2020 at 02:39:14PM +0800, sherry sun wrote: > > From: Sherry Sun <sherry.sun@nxp.com> > > > > Add documentation for i.MX8MP DDRC binding based on synopsys_edac > doc, > > which use the same memory-controller IP. > > > > Signed-off-by: Sherry Sun <sherry.sun@nxp.com> > > --- > > .../devicetree/bindings/memory-controllers/synopsys.txt | 8 ++++++-- > > 1 file changed, 6 insertions(+), 2 deletions(-) > > > > diff --git > > a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > > b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > > index 9d32762c47e1..5c03959a451f 100644 > > --- > > a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt > > +++ b/Documentation/devicetree/bindings/memory- > controllers/synopsys.tx > > +++ t > > @@ -6,16 +6,20 @@ bus width configurations. > > The Zynq DDR ECC controller has an optional ECC support in half-bus > > width > > (16-bit) configuration. > > > > -These both ECC controllers correct single bit ECC errors and detect > > double bit > > +The i.MX8MP DDR ECC controller has an ECC support in 64-bit bus width > > +configurations. > > + > > +These all ECC controllers correct single bit ECC errors and detect > > +double bit > > All the ECC... > > With that, > > Reviewed-by: Rob Herring <robh@kernel.org> Thanks, I will correct it. Best regards Sherry Sun > > > ECC errors. > > > > Required properties: > > - compatible: One of: > > - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller > > - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller > > + - 'fsl,imx8mp-ddrc' : i.MX8MP DDR ECC controller > > - reg: Should contain DDR controller registers location and length. > > > > -Required properties for "xlnx,zynqmp-ddrc-2.40a": > > +Required properties for "xlnx,zynqmp-ddrc-2.40a" and "fsl,imx8mp-ddrc": > > - interrupts: Property with a value describing the interrupt number. > > > > Example: > > -- > > 2.17.1 > >
diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt index 9d32762c47e1..5c03959a451f 100644 --- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt +++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt @@ -6,16 +6,20 @@ bus width configurations. The Zynq DDR ECC controller has an optional ECC support in half-bus width (16-bit) configuration. -These both ECC controllers correct single bit ECC errors and detect double bit +The i.MX8MP DDR ECC controller has an ECC support in 64-bit bus width +configurations. + +These all ECC controllers correct single bit ECC errors and detect double bit ECC errors. Required properties: - compatible: One of: - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller + - 'fsl,imx8mp-ddrc' : i.MX8MP DDR ECC controller - reg: Should contain DDR controller registers location and length. -Required properties for "xlnx,zynqmp-ddrc-2.40a": +Required properties for "xlnx,zynqmp-ddrc-2.40a" and "fsl,imx8mp-ddrc": - interrupts: Property with a value describing the interrupt number. Example: