Message ID | 20200226163054.9509-1-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | drm/i915: Set up PIPE_MISC truncate bit on tgl+ | expand |
On Wed, 2020-02-26 at 18:30 +0200, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Looks like the pipe rounding mode bit has moved from PIPE_CHICKEN to > PIPE_MISC on tgl. Frob the new location. > > Bspec does still document the old bits as well, so I left the code > for them as is until we get clarification from the hw folks on > whether the old bits still do something useful. Matches Bspec, please CC me in the future patch removing the old bit if needed. Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 +++ > drivers/gpu/drm/i915/i915_reg.h | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 2fd3ccd33e30..4e8744c15f4b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -10139,6 +10139,9 @@ static void bdw_set_pipemisc(const struct > intel_crtc_state *crtc_state) > BIT(PLANE_CURSOR))) == 0) > val |= PIPEMISC_HDR_MODE_PRECISION; > > + if (INTEL_GEN(dev_priv) >= 12) > + val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; > + > intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); > } > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index f45b5e86ec63..133c48311649 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5889,6 +5889,7 @@ enum { > #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */ > #define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */ > #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11) > +#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ > #define PIPEMISC_DITHER_BPC_MASK (7 << 5) > #define PIPEMISC_DITHER_8_BPC (0 << 5) > #define PIPEMISC_DITHER_10_BPC (1 << 5)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 2fd3ccd33e30..4e8744c15f4b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -10139,6 +10139,9 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) BIT(PLANE_CURSOR))) == 0) val |= PIPEMISC_HDR_MODE_PRECISION; + if (INTEL_GEN(dev_priv) >= 12) + val |= PIPEMISC_PIXEL_ROUNDING_TRUNC; + intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f45b5e86ec63..133c48311649 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5889,6 +5889,7 @@ enum { #define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */ #define PIPEMISC_HDR_MODE_PRECISION (1 << 23) /* icl+ */ #define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11) +#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */ #define PIPEMISC_DITHER_BPC_MASK (7 << 5) #define PIPEMISC_DITHER_8_BPC (0 << 5) #define PIPEMISC_DITHER_10_BPC (1 << 5)