| Message ID | 20200226203455.23032-13-imre.deak@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | drm/i915: Clean up DPLL output/refclock tracking | expand |
On Wed, Feb 26, 2020 at 10:34:54PM +0200, Imre Deak wrote: > Instead of reading out the WRPLL/SPLL control values from HW, we can use > the DPLL state that was already read out, or swapped-to. > > Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index b87b4ff5de52..7e6da58a47c9 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -880,13 +880,10 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, > static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, > const struct intel_shared_dpll *pll) > { > - i915_reg_t reg = pll->info->id == DPLL_ID_WRPLL1 ? > - WRPLL_CTL(0) : WRPLL_CTL(1); > int refclk; > int n, p, r; > - u32 wrpll; > + u32 wrpll = pll->state.hw_state.wrpll; > > - wrpll = intel_de_read(dev_priv, reg); > switch (wrpll & WRPLL_REF_MASK) { > case WRPLL_REF_SPECIAL_HSW: > /* > @@ -1003,7 +1000,7 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915, > { > int link_clock = 0; > > - switch (intel_de_read(i915, SPLL_CTL) & SPLL_FREQ_MASK) { > + switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) { > case SPLL_FREQ_810MHz: > link_clock = 81000; > break; > -- > 2.23.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index b87b4ff5de52..7e6da58a47c9 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -880,13 +880,10 @@ hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state, static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv, const struct intel_shared_dpll *pll) { - i915_reg_t reg = pll->info->id == DPLL_ID_WRPLL1 ? - WRPLL_CTL(0) : WRPLL_CTL(1); int refclk; int n, p, r; - u32 wrpll; + u32 wrpll = pll->state.hw_state.wrpll; - wrpll = intel_de_read(dev_priv, reg); switch (wrpll & WRPLL_REF_MASK) { case WRPLL_REF_SPECIAL_HSW: /* @@ -1003,7 +1000,7 @@ static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915, { int link_clock = 0; - switch (intel_de_read(i915, SPLL_CTL) & SPLL_FREQ_MASK) { + switch (pll->state.hw_state.spll & SPLL_FREQ_MASK) { case SPLL_FREQ_810MHz: link_clock = 81000; break;
Instead of reading out the WRPLL/SPLL control values from HW, we can use the DPLL state that was already read out, or swapped-to. Signed-off-by: Imre Deak <imre.deak@intel.com> --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-)