ARM: dts: dra7: Add bus_dma_limit for L3 bus

Message ID	20200310115309.31354-1-rogerq@ti.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=sshs=43=vger.kernel.org=linux-omap-owner@kernel.org> From: Roger Quadros <rogerq@ti.com> To: <tony@atomide.com> CC: <hch@lst.de>, <robin.murphy@arm.com>, <robh+dt@kernel.org>, <nm@ti.com>, <t-kristo@ti.com>, <nsekhar@ti.com>, <linux-omap@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Roger Quadros <rogerq@ti.com> Subject: [PATCH] ARM: dts: dra7: Add bus_dma_limit for L3 bus Date: Tue, 10 Mar 2020 13:53:09 +0200 Message-ID: <20200310115309.31354-1-rogerq@ti.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-omap-owner@vger.kernel.org Precedence: bulk
Series	ARM: dts: dra7: Add bus_dma_limit for L3 bus \| expand ARM: dts: dra7: Add bus_dma_limit for L3 bus

Roger Quadros March 10, 2020, 11:53 a.m. UTC

The L3 interconnect can access only 32-bits of address.
Add the dma-ranges property to reflect this limit.

This will ensure that no device under L3 is
given > 32-bit address for DMA.

Issue was observed only with SATA on DRA7-EVM with 4GB RAM
and CONFIG_ARM_LPAE enabled. This is because the controller
can perform 64-bit DMA and was setting the dma_mask to 64-bit.

Setting the correct bus_dma_limit fixes the issue.

Signed-off-by: Roger Quadros <rogerq@ti.com>
---
 arch/arm/boot/dts/dra7-l4.dtsi |  20 ++---
 arch/arm/boot/dts/dra7.dtsi    | 129 +++++++++++++++++----------------
 arch/arm/boot/dts/dra72x.dtsi  |   6 +-
 arch/arm/boot/dts/dra74x.dtsi  |  33 +++++----
 4 files changed, 95 insertions(+), 93 deletions(-)

Tero Kristo March 10, 2020, 2:45 p.m. UTC | #1

On 10/03/2020 13:53, Roger Quadros wrote:
> The L3 interconnect can access only 32-bits of address.
> Add the dma-ranges property to reflect this limit.
> 
> This will ensure that no device under L3 is
> given > 32-bit address for DMA.
> 
> Issue was observed only with SATA on DRA7-EVM with 4GB RAM
> and CONFIG_ARM_LPAE enabled. This is because the controller
> can perform 64-bit DMA and was setting the dma_mask to 64-bit.
> 
> Setting the correct bus_dma_limit fixes the issue.

This seems kind of messy to modify almost every DT node because of 
this.... Are you sure this is the only way to get it done? No way to 
modify the sata node only which is impacted somehow?

Also, what if you just pass 0xffffffff to the dma-ranges property? That 
would avoid modifying every node I guess.

-Tero

> 
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
>   arch/arm/boot/dts/dra7-l4.dtsi |  20 ++---
>   arch/arm/boot/dts/dra7.dtsi    | 129 +++++++++++++++++----------------
>   arch/arm/boot/dts/dra72x.dtsi  |   6 +-
>   arch/arm/boot/dts/dra74x.dtsi  |  33 +++++----
>   4 files changed, 95 insertions(+), 93 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
> index fc418834890d..5bbe3de7eba3 100644
> --- a/arch/arm/boot/dts/dra7-l4.dtsi
> +++ b/arch/arm/boot/dts/dra7-l4.dtsi
> @@ -2280,11 +2280,11 @@
>   
>   &l4_per2 {						/* 0x48400000 */
>   	compatible = "ti,dra7-l4-per2", "simple-bus";
> -	reg = <0x48400000 0x800>,
> -	      <0x48400800 0x800>,
> -	      <0x48401000 0x400>,
> -	      <0x48401400 0x400>,
> -	      <0x48401800 0x400>;
> +	reg = <0x48400000 0x0 0x800>,
> +	      <0x48400800 0x0 0x800>,
> +	      <0x48401000 0x0 0x400>,
> +	      <0x48401400 0x0 0x400>,
> +	      <0x48401800 0x0 0x400>;
>   	reg-names = "ap", "la", "ia0", "ia1", "ia2";
>   	#address-cells = <1>;
>   	#size-cells = <1>;
> @@ -3152,11 +3152,11 @@
>   
>   &l4_per3 {						/* 0x48800000 */
>   	compatible = "ti,dra7-l4-per3", "simple-bus";
> -	reg = <0x48800000 0x800>,
> -	      <0x48800800 0x800>,
> -	      <0x48801000 0x400>,
> -	      <0x48801400 0x400>,
> -	      <0x48801800 0x400>;
> +	reg = <0x48800000 0x0 0x800>,
> +	      <0x48800800 0x0 0x800>,
> +	      <0x48801000 0x0 0x400>,
> +	      <0x48801400 0x0 0x400>,
> +	      <0x48801800 0x0 0x400>;
>   	reg-names = "ap", "la", "ia0", "ia1", "ia2";
>   	#address-cells = <1>;
>   	#size-cells = <1>;
> diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
> index d78b684e7fca..81e7f30afe02 100644
> --- a/arch/arm/boot/dts/dra7.dtsi
> +++ b/arch/arm/boot/dts/dra7.dtsi
> @@ -146,8 +146,9 @@
>   	ocp {
>   		compatible = "ti,dra7-l3-noc", "simple-bus";
>   		#address-cells = <1>;
> -		#size-cells = <1>;
> -		ranges = <0x0 0x0 0x0 0xc0000000>;
> +		#size-cells = <2>;
> +		ranges = <0x0 0x0 0x0 0x0 0xc0000000>;
> +		dma-ranges = <0x0 0x0 0x0 0x1 0x00000000>;
>   		ti,hwmods = "l3_main_1", "l3_main_2";
>   		reg = <0x0 0x44000000 0x0 0x1000000>,
>   		      <0x0 0x45000000 0x0 0x1000>;
> @@ -261,7 +262,7 @@
>   
>   		ocmcram1: ocmcram@40300000 {
>   			compatible = "mmio-sram";
> -			reg = <0x40300000 0x80000>;
> +			reg = <0x40300000 0x0 0x80000>;
>   			ranges = <0x0 0x40300000 0x80000>;
>   			#address-cells = <1>;
>   			#size-cells = <1>;
> @@ -291,7 +292,7 @@
>   		ocmcram2: ocmcram@40400000 {
>   			status = "disabled";
>   			compatible = "mmio-sram";
> -			reg = <0x40400000 0x100000>;
> +			reg = <0x40400000 0x0 0x100000>;
>   			ranges = <0x0 0x40400000 0x100000>;
>   			#address-cells = <1>;
>   			#size-cells = <1>;
> @@ -300,19 +301,19 @@
>   		ocmcram3: ocmcram@40500000 {
>   			status = "disabled";
>   			compatible = "mmio-sram";
> -			reg = <0x40500000 0x100000>;
> +			reg = <0x40500000 0x0 0x100000>;
>   			ranges = <0x0 0x40500000 0x100000>;
>   			#address-cells = <1>;
>   			#size-cells = <1>;
>   		};
>   
>   		bandgap: bandgap@4a0021e0 {
> -			reg = <0x4a0021e0 0xc
> -				0x4a00232c 0xc
> -				0x4a002380 0x2c
> -				0x4a0023C0 0x3c
> -				0x4a002564 0x8
> -				0x4a002574 0x50>;
> +			reg = <0x4a0021e0 0x0 0xc
> +				0x4a00232c 0x0 0xc
> +				0x4a002380 0x0 0x2c
> +				0x4a0023C0 0x0 0x3c
> +				0x4a002564 0x0 0x8
> +				0x4a002574 0x0 0x50>;
>   				compatible = "ti,dra752-bandgap";
>   				interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
>   				#thermal-sensor-cells = <1>;
> @@ -320,12 +321,12 @@
>   
>   		dsp1_system: dsp_system@40d00000 {
>   			compatible = "syscon";
> -			reg = <0x40d00000 0x100>;
> +			reg = <0x40d00000 0x0 0x100>;
>   		};
>   
>   		dra7_iodelay_core: padconf@4844a000 {
>   			compatible = "ti,dra7-iodelay";
> -			reg = <0x4844a000 0x0d1c>;
> +			reg = <0x4844a000 0x0 0x0d1c>;
>   			#address-cells = <1>;
>   			#size-cells = <0>;
>   			#pinctrl-cells = <2>;
> @@ -334,7 +335,7 @@
>   		edma: edma@43300000 {
>   			compatible = "ti,edma3-tpcc";
>   			ti,hwmods = "tpcc";
> -			reg = <0x43300000 0x100000>;
> +			reg = <0x43300000 0x0 0x100000>;
>   			reg-names = "edma3_cc";
>   			interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
>   				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
> @@ -357,7 +358,7 @@
>   		edma_tptc0: tptc@43400000 {
>   			compatible = "ti,edma3-tptc";
>   			ti,hwmods = "tptc0";
> -			reg =	<0x43400000 0x100000>;
> +			reg =	<0x43400000 0x0 0x100000>;
>   			interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
>   			interrupt-names = "edma3_tcerrint";
>   		};
> @@ -365,23 +366,23 @@
>   		edma_tptc1: tptc@43500000 {
>   			compatible = "ti,edma3-tptc";
>   			ti,hwmods = "tptc1";
> -			reg =	<0x43500000 0x100000>;
> +			reg =	<0x43500000 0x0 0x100000>;
>   			interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
>   			interrupt-names = "edma3_tcerrint";
>   		};
>   
>   		dmm@4e000000 {
>   			compatible = "ti,omap5-dmm";
> -			reg = <0x4e000000 0x800>;
> +			reg = <0x4e000000 0x0 0x800>;
>   			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
>   			ti,hwmods = "dmm";
>   		};
>   
>   		target-module@40d01000 {
>   			compatible = "ti,sysc-omap2", "ti,sysc";
> -			reg = <0x40d01000 0x4>,
> -			      <0x40d01010 0x4>,
> -			      <0x40d01014 0x4>;
> +			reg = <0x40d01000 0x0 0x4>,
> +			      <0x40d01010 0x0 0x4>,
> +			      <0x40d01014 0x0 0x4>;
>   			reg-names = "rev", "sysc", "syss";
>   			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
>   					<SYSC_IDLE_NO>,
> @@ -408,9 +409,9 @@
>   
>   		target-module@40d02000 {
>   			compatible = "ti,sysc-omap2", "ti,sysc";
> -			reg = <0x40d02000 0x4>,
> -			      <0x40d02010 0x4>,
> -			      <0x40d02014 0x4>;
> +			reg = <0x40d02000 0x0 0x4>,
> +			      <0x40d02010 0x0 0x4>,
> +			      <0x40d02014 0x0 0x4>;
>   			reg-names = "rev", "sysc", "syss";
>   			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
>   					<SYSC_IDLE_NO>,
> @@ -437,9 +438,9 @@
>   
>   		target-module@58882000 {
>   			compatible = "ti,sysc-omap2", "ti,sysc";
> -			reg = <0x58882000 0x4>,
> -			      <0x58882010 0x4>,
> -			      <0x58882014 0x4>;
> +			reg = <0x58882000 0x0 0x4>,
> +			      <0x58882010 0x0 0x4>,
> +			      <0x58882014 0x0 0x4>;
>   			reg-names = "rev", "sysc", "syss";
>   			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
>   					<SYSC_IDLE_NO>,
> @@ -466,9 +467,9 @@
>   
>   		target-module@55082000 {
>   			compatible = "ti,sysc-omap2", "ti,sysc";
> -			reg = <0x55082000 0x4>,
> -			      <0x55082010 0x4>,
> -			      <0x55082014 0x4>;
> +			reg = <0x55082000 0x0 0x4>,
> +			      <0x55082010 0x0 0x4>,
> +			      <0x55082014 0x0 0x4>;
>   			reg-names = "rev", "sysc", "syss";
>   			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
>   					<SYSC_IDLE_NO>,
> @@ -502,9 +503,9 @@
>   			ti,settling-time = <50>;
>   			ti,clock-cycles = <16>;
>   
> -			reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
> -			      <0x4ae06014 0x4>, <0x4a003b20 0xc>,
> -			      <0x4ae0c158 0x4>;
> +			reg = <0x4ae07ddc 0x0 0x4>, <0x4ae07de0 0x0 0x4>,
> +			      <0x4ae06014 0x0 0x4>, <0x4a003b20 0x0 0xc>,
> +			      <0x4ae0c158 0x0 0x4>;
>   			reg-names = "setup-address", "control-address",
>   				    "int-address", "efuse-address",
>   				    "ldo-address";
> @@ -535,9 +536,9 @@
>   			ti,settling-time = <50>;
>   			ti,clock-cycles = <16>;
>   
> -			reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
> -			      <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
> -			      <0x4a002470 0x4>;
> +			reg = <0x4ae07e34 0x0 0x4>, <0x4ae07e24 0x0 0x4>,
> +			      <0x4ae06010 0x0 0x4>, <0x4a0025cc 0x0 0xc>,
> +			      <0x4a002470 0x0 0x4>;
>   			reg-names = "setup-address", "control-address",
>   				    "int-address", "efuse-address",
>   				    "ldo-address";
> @@ -568,9 +569,9 @@
>   			ti,settling-time = <50>;
>   			ti,clock-cycles = <16>;
>   
> -			reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
> -			      <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
> -			      <0x4a00246c 0x4>;
> +			reg = <0x4ae07e30 0x0 0x4>, <0x4ae07e20 0x0 0x4>,
> +			      <0x4ae06010 0x0 0x4>, <0x4a0025e0 0x0 0xc>,
> +			      <0x4a00246c 0x0 0x4>;
>   			reg-names = "setup-address", "control-address",
>   				    "int-address", "efuse-address",
>   				    "ldo-address";
> @@ -601,9 +602,9 @@
>   			ti,settling-time = <50>;
>   			ti,clock-cycles = <16>;
>   
> -			reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
> -			      <0x4ae06010 0x4>, <0x4a003b08 0xc>,
> -			      <0x4ae0c154 0x4>;
> +			reg = <0x4ae07de4 0x0 0x4>, <0x4ae07de8 0x0 0x4>,
> +			      <0x4ae06010 0x0 0x4>, <0x4a003b08 0x0 0xc>,
> +			      <0x4ae0c154 0x0 0x4>;
>   			reg-names = "setup-address", "control-address",
>   				    "int-address", "efuse-address",
>   				    "ldo-address";
> @@ -627,8 +628,8 @@
>   
>   		qspi: spi@4b300000 {
>   			compatible = "ti,dra7xxx-qspi";
> -			reg = <0x4b300000 0x100>,
> -			      <0x5c000000 0x4000000>;
> +			reg = <0x4b300000 0x0 0x100>,
> +			      <0x5c000000 0x0 0x4000000>;
>   			reg-names = "qspi_base", "qspi_mmap";
>   			syscon-chipselects = <&scm_conf 0x558>;
>   			#address-cells = <1>;
> @@ -644,7 +645,7 @@
>   		/* OCP2SCP3 */
>   		sata: sata@4a141100 {
>   			compatible = "snps,dwc-ahci";
> -			reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
> +			reg = <0x4a140000 0x0 0x1100>, <0x4a141100 0x0 0x7>;
>   			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
>   			phys = <&sata_phy>;
>   			phy-names = "sata-phy";
> @@ -658,7 +659,7 @@
>   		gpmc: gpmc@50000000 {
>   			compatible = "ti,am3352-gpmc";
>   			ti,hwmods = "gpmc";
> -			reg = <0x50000000 0x37c>;      /* device IO registers */
> +			reg = <0x50000000 0x0 0x37c>;      /* device IO registers */
>   			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
>   			dmas = <&edma_xbar 4 0>;
>   			dma-names = "rxtx";
> @@ -675,8 +676,8 @@
>   
>   		target-module@56000000 {
>   			compatible = "ti,sysc-omap4", "ti,sysc";
> -			reg = <0x5600fe00 0x4>,
> -			      <0x5600fe10 0x4>;
> +			reg = <0x5600fe00 0x0 0x4>,
> +			      <0x5600fe10 0x0 0x4>;
>   			reg-names = "rev", "sysc";
>   			ti,sysc-midle = <SYSC_IDLE_FORCE>,
>   					<SYSC_IDLE_NO>,
> @@ -693,7 +694,7 @@
>   
>   		crossbar_mpu: crossbar@4a002a48 {
>   			compatible = "ti,irq-crossbar";
> -			reg = <0x4a002a48 0x130>;
> +			reg = <0x4a002a48 0x0 0x130>;
>   			interrupt-controller;
>   			interrupt-parent = <&wakeupgen>;
>   			#interrupt-cells = <3>;
> @@ -715,11 +716,11 @@
>   			syscon-pll-ctrl = <&scm_conf 0x538>;
>   			#address-cells = <1>;
>   			#size-cells = <1>;
> -			ranges;
> +			ranges = <0x0 0x58000000 0x79000>;
>   
>   			dispc@58001000 {
>   				compatible = "ti,dra7-dispc";
> -				reg = <0x58001000 0x1000>;
> +				reg = <0x1000 0x1000>;
>   				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
>   				ti,hwmods = "dss_dispc";
>   				clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
> @@ -730,10 +731,10 @@
>   
>   			hdmi: encoder@58060000 {
>   				compatible = "ti,dra7-hdmi";
> -				reg = <0x58040000 0x200>,
> -				      <0x58040200 0x80>,
> -				      <0x58040300 0x80>,
> -				      <0x58060000 0x19000>;
> +				reg = <0x40000 0x200>,
> +				      <0x40200 0x80>,
> +				      <0x40300 0x80>,
> +				      <0x60000 0x19000>;
>   				reg-names = "wp", "pll", "phy", "core";
>   				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
>   				status = "disabled";
> @@ -748,9 +749,9 @@
>   
>   		aes1_target: target-module@4b500000 {
>   			compatible = "ti,sysc-omap2", "ti,sysc";
> -			reg = <0x4b500080 0x4>,
> -			      <0x4b500084 0x4>,
> -			      <0x4b500088 0x4>;
> +			reg = <0x4b500080 0x0 0x4>,
> +			      <0x4b500084 0x0 0x4>,
> +			      <0x4b500088 0x0 0x4>;
>   			reg-names = "rev", "sysc", "syss";
>   			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
>   					 SYSC_OMAP2_AUTOIDLE)>;
> @@ -779,9 +780,9 @@
>   
>   		aes2_target: target-module@4b700000 {
>   			compatible = "ti,sysc-omap2", "ti,sysc";
> -			reg = <0x4b700080 0x4>,
> -			      <0x4b700084 0x4>,
> -			      <0x4b700088 0x4>;
> +			reg = <0x4b700080 0x0 0x4>,
> +			      <0x4b700084 0x0 0x4>,
> +			      <0x4b700088 0x0 0x4>;
>   			reg-names = "rev", "sysc", "syss";
>   			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
>   					 SYSC_OMAP2_AUTOIDLE)>;
> @@ -810,9 +811,9 @@
>   
>   		sham_target: target-module@4b101000 {
>   			compatible = "ti,sysc-omap3-sham", "ti,sysc";
> -			reg = <0x4b101100 0x4>,
> -			      <0x4b101110 0x4>,
> -			      <0x4b101114 0x4>;
> +			reg = <0x4b101100 0x0 0x4>,
> +			      <0x4b101110 0x0 0x4>,
> +			      <0x4b101114 0x0 0x4>;
>   			reg-names = "rev", "sysc", "syss";
>   			ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
>   					 SYSC_OMAP2_AUTOIDLE)>;
> @@ -840,7 +841,7 @@
>   
>   		opp_supply_mpu: opp-supply@4a003b20 {
>   			compatible = "ti,omap5-opp-supply";
> -			reg = <0x4a003b20 0xc>;
> +			reg = <0x4a003b20 0x0 0xc>;
>   			ti,efuse-settings = <
>   			/* uV   offset */
>   			1060000 0x0
> diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
> index 82b57a35abc0..09c1801c18c3 100644
> --- a/arch/arm/boot/dts/dra72x.dtsi
> +++ b/arch/arm/boot/dts/dra72x.dtsi
> @@ -60,9 +60,9 @@
>   };
>   
>   &dss {
> -	reg = <0x58000000 0x80>,
> -	      <0x58004054 0x4>,
> -	      <0x58004300 0x20>;
> +	reg = <0x58000000 0x0 0x80>,
> +	      <0x58004054 0x0 0x4>,
> +	      <0x58004300 0x0 0x20>;
>   	reg-names = "dss", "pll1_clkctrl", "pll1";
>   
>   	clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>,
> diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
> index c5abc436ca1f..a88a64af41e0 100644
> --- a/arch/arm/boot/dts/dra74x.dtsi
> +++ b/arch/arm/boot/dts/dra74x.dtsi
> @@ -39,22 +39,23 @@
>   	ocp {
>   		dsp2_system: dsp_system@41500000 {
>   			compatible = "syscon";
> -			reg = <0x41500000 0x100>;
> +			reg = <0x41500000 0x0 0x100>;
>   		};
>   
>   		omap_dwc3_4: omap_dwc3_4@48940000 {
>   			compatible = "ti,dwc3";
>   			ti,hwmods = "usb_otg_ss4";
> -			reg = <0x48940000 0x10000>;
> +			reg = <0x48940000 0x0 0x10000>;
>   			interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
>   			#address-cells = <1>;
>   			#size-cells = <1>;
>   			utmi-mode = <2>;
> -			ranges;
> +			ranges = <0x0 0x48940000 0x20000>;
>   			status = "disabled";
> -			usb4: usb@48950000 {
> +
> +			usb4: usb@10000 {
>   				compatible = "snps,dwc3";
> -				reg = <0x48950000 0x17000>;
> +				reg = <0x10000 0x17000>;
>   				interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
>   					     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
>   					     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
> @@ -68,9 +69,9 @@
>   
>   		target-module@41501000 {
>   			compatible = "ti,sysc-omap2", "ti,sysc";
> -			reg = <0x41501000 0x4>,
> -			      <0x41501010 0x4>,
> -			      <0x41501014 0x4>;
> +			reg = <0x41501000 0x0 0x4>,
> +			      <0x41501010 0x0 0x4>,
> +			      <0x41501014 0x0 0x4>;
>   			reg-names = "rev", "sysc", "syss";
>   			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
>   					<SYSC_IDLE_NO>,
> @@ -97,9 +98,9 @@
>   
>   		target-module@41502000 {
>   			compatible = "ti,sysc-omap2", "ti,sysc";
> -			reg = <0x41502000 0x4>,
> -			      <0x41502010 0x4>,
> -			      <0x41502014 0x4>;
> +			reg = <0x41502000 0x0 0x4>,
> +			      <0x41502010 0x0 0x4>,
> +			      <0x41502014 0x0 0x4>;
>   			reg-names = "rev", "sysc", "syss";
>   			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
>   					<SYSC_IDLE_NO>,
> @@ -132,11 +133,11 @@
>   };
>   
>   &dss {
> -	reg = <0x58000000 0x80>,
> -	      <0x58004054 0x4>,
> -	      <0x58004300 0x20>,
> -	      <0x58009054 0x4>,
> -	      <0x58009300 0x20>;
> +	reg = <0x58000000 0x0 0x80>,
> +	      <0x58004054 0x0 0x4>,
> +	      <0x58004300 0x0 0x20>,
> +	      <0x58009054 0x0 0x4>,
> +	      <0x58009300 0x0 0x20>;
>   	reg-names = "dss", "pll1_clkctrl", "pll1",
>   		    "pll2_clkctrl", "pll2";
>   
> 

--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki

Tony Lindgren March 10, 2020, 3:48 p.m. UTC | #2

* Tero Kristo <t-kristo@ti.com> [200310 14:46]:
> On 10/03/2020 13:53, Roger Quadros wrote:
> > The L3 interconnect can access only 32-bits of address.
> > Add the dma-ranges property to reflect this limit.
> > 
> > This will ensure that no device under L3 is
> > given > 32-bit address for DMA.
> > 
> > Issue was observed only with SATA on DRA7-EVM with 4GB RAM
> > and CONFIG_ARM_LPAE enabled. This is because the controller
> > can perform 64-bit DMA and was setting the dma_mask to 64-bit.
> > 
> > Setting the correct bus_dma_limit fixes the issue.
> 
> This seems kind of messy to modify almost every DT node because of this....
> Are you sure this is the only way to get it done? No way to modify the sata
> node only which is impacted somehow?
> 
> Also, what if you just pass 0xffffffff to the dma-ranges property? That
> would avoid modifying every node I guess.

Also, I think these interconnects are not limited to 32-bit access.
So yeah I too would prefer a top level dma-ranges property assuming
that works.

I guess there dma-ranges should not be 0xffffffff though if
limited to 2GB :)

Regards,

Tony

Robin Murphy March 10, 2020, 4:16 p.m. UTC | #3

On 10/03/2020 3:48 pm, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [200310 14:46]:
>> On 10/03/2020 13:53, Roger Quadros wrote:
>>> The L3 interconnect can access only 32-bits of address.
>>> Add the dma-ranges property to reflect this limit.
>>>
>>> This will ensure that no device under L3 is
>>> given > 32-bit address for DMA.
>>>
>>> Issue was observed only with SATA on DRA7-EVM with 4GB RAM
>>> and CONFIG_ARM_LPAE enabled. This is because the controller
>>> can perform 64-bit DMA and was setting the dma_mask to 64-bit.
>>>
>>> Setting the correct bus_dma_limit fixes the issue.
>>
>> This seems kind of messy to modify almost every DT node because of this....
>> Are you sure this is the only way to get it done? No way to modify the sata
>> node only which is impacted somehow?
>>
>> Also, what if you just pass 0xffffffff to the dma-ranges property? That
>> would avoid modifying every node I guess.
> 
> Also, I think these interconnects are not limited to 32-bit access.
> So yeah I too would prefer a top level dma-ranges property assuming
> that works.
> 
> I guess there dma-ranges should not be 0xffffffff though if
> limited to 2GB :)

It should work fine to just describe the Q3 and Q4 DDR regions as the 
DMA range, i.e.:

	ocp {
		...
		dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
		...
	};

That would certainly be far less invasive :)

Robin.

Roger Quadros March 11, 2020, 7:13 a.m. UTC | #4

On 10/03/2020 18:16, Robin Murphy wrote:
> On 10/03/2020 3:48 pm, Tony Lindgren wrote:
>> * Tero Kristo <t-kristo@ti.com> [200310 14:46]:
>>> On 10/03/2020 13:53, Roger Quadros wrote:
>>>> The L3 interconnect can access only 32-bits of address.
>>>> Add the dma-ranges property to reflect this limit.
>>>>
>>>> This will ensure that no device under L3 is
>>>> given > 32-bit address for DMA.
>>>>
>>>> Issue was observed only with SATA on DRA7-EVM with 4GB RAM
>>>> and CONFIG_ARM_LPAE enabled. This is because the controller
>>>> can perform 64-bit DMA and was setting the dma_mask to 64-bit.
>>>>
>>>> Setting the correct bus_dma_limit fixes the issue.
>>>
>>> This seems kind of messy to modify almost every DT node because of this....
>>> Are you sure this is the only way to get it done? No way to modify the sata
>>> node only which is impacted somehow?
>>>
>>> Also, what if you just pass 0xffffffff to the dma-ranges property? That
>>> would avoid modifying every node I guess.
>>
>> Also, I think these interconnects are not limited to 32-bit access.
>> So yeah I too would prefer a top level dma-ranges property assuming
>> that works.
>>
>> I guess there dma-ranges should not be 0xffffffff though if
>> limited to 2GB :)

Right, and the code expects it to not look like a mask.
 From of_dma_configure()

         ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
	..
                 if (size & 1) {
                        dev_warn(dev, "Invalid size 0x%llx for dma-range\n",
                                  size);
                        size = size + 1;
                 }

> 
> It should work fine to just describe the Q3 and Q4 DDR regions as the DMA range, i.e.:
> 
>      ocp {
>          ...
>          dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
>          ...
>      };
> 
> That would certainly be far less invasive :)

This is brilliant! Thanks :)

Roger Quadros March 11, 2020, 7:20 a.m. UTC | #5

On 10/03/2020 17:48, Tony Lindgren wrote:
> * Tero Kristo <t-kristo@ti.com> [200310 14:46]:
>> On 10/03/2020 13:53, Roger Quadros wrote:
>>> The L3 interconnect can access only 32-bits of address.
>>> Add the dma-ranges property to reflect this limit.
>>>
>>> This will ensure that no device under L3 is
>>> given > 32-bit address for DMA.
>>>
>>> Issue was observed only with SATA on DRA7-EVM with 4GB RAM
>>> and CONFIG_ARM_LPAE enabled. This is because the controller
>>> can perform 64-bit DMA and was setting the dma_mask to 64-bit.
>>>
>>> Setting the correct bus_dma_limit fixes the issue.
>>
>> This seems kind of messy to modify almost every DT node because of this....
>> Are you sure this is the only way to get it done? No way to modify the sata
>> node only which is impacted somehow?
>>
>> Also, what if you just pass 0xffffffff to the dma-ranges property? That
>> would avoid modifying every node I guess.
> 
> Also, I think these interconnects are not limited to 32-bit access.

But from Table 2-1. L3_MAIN Memory Map

Start address	0x0000_0000
End address	0xFFFF_FFFF

So it is 32-bit limit, right?

> So yeah I too would prefer a top level dma-ranges property assuming
> that works.
> 
> I guess there dma-ranges should not be 0xffffffff though if
> limited to 2GB :)
> 
> Regards,
> 
> Tony
>

Roger Quadros March 11, 2020, 10:28 a.m. UTC | #6

On 11/03/2020 09:13, Roger Quadros wrote:
> 
> 
> On 10/03/2020 18:16, Robin Murphy wrote:
>> On 10/03/2020 3:48 pm, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [200310 14:46]:
>>>> On 10/03/2020 13:53, Roger Quadros wrote:
>>>>> The L3 interconnect can access only 32-bits of address.
>>>>> Add the dma-ranges property to reflect this limit.
>>>>>
>>>>> This will ensure that no device under L3 is
>>>>> given > 32-bit address for DMA.
>>>>>
>>>>> Issue was observed only with SATA on DRA7-EVM with 4GB RAM
>>>>> and CONFIG_ARM_LPAE enabled. This is because the controller
>>>>> can perform 64-bit DMA and was setting the dma_mask to 64-bit.
>>>>>
>>>>> Setting the correct bus_dma_limit fixes the issue.
>>>>
>>>> This seems kind of messy to modify almost every DT node because of this....
>>>> Are you sure this is the only way to get it done? No way to modify the sata
>>>> node only which is impacted somehow?
>>>>
>>>> Also, what if you just pass 0xffffffff to the dma-ranges property? That
>>>> would avoid modifying every node I guess.
>>>
>>> Also, I think these interconnects are not limited to 32-bit access.
>>> So yeah I too would prefer a top level dma-ranges property assuming
>>> that works.
>>>
>>> I guess there dma-ranges should not be 0xffffffff though if
>>> limited to 2GB :)
> 
> Right, and the code expects it to not look like a mask.
>  From of_dma_configure()
> 
>          ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
>      ..
>                  if (size & 1) {
>                         dev_warn(dev, "Invalid size 0x%llx for dma-range\n",
>                                   size);
>                         size = size + 1;
>                  }
> 
>>
>> It should work fine to just describe the Q3 and Q4 DDR regions as the DMA range, i.e.:
>>
>>      ocp {
>>          ...
>>          dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
>>          ...
>>      };
>>
>> That would certainly be far less invasive :)
> 
> This is brilliant! Thanks :)
> 

I noticed that all devices are not getting the right bus_dma_limit (see kernel log at end).

At least the following devices should be fixed right? Any other devices I missed?

[    1.264194] omap-dma-engine 4a056000.dma-controller: coherent_dma_mask ffffffff bus_dma_limit 0

[    4.583356] omap-iommu 40d01000.mmu: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.605865] omap-iommu 40d02000.mmu: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.659729] omap-iommu 55082000.mmu: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.682122] omap-iommu 41501000.mmu: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.704553] omap-iommu 41502000.mmu: coherent_dma_mask ffffffff bus_dma_limit 0

[    4.234731] sdhci-omap 4809c000.mmc: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.257030] sdhci-omap 480b4000.mmc: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.298030] sdhci-omap 480d1000.mmc: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.562873] dra7-pcie 51000000.pcie: coherent_dma_mask ffffffff bus_dma_limit 0

[   10.944741] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask ffffffff bus_dma_limit 0
[   10.955211] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask ffffffff bus_dma_limit 0

cheers,
-roger


full list

[    0.286523] omap_l3_noc 44000000.ocp: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    0.323023] sram 40300000.ocmcram: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    0.365861] edma3-tptc 43400000.tptc: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    0.374205] edma3-tptc 43500000.tptc: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    0.382739] edma 43300000.edma: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    0.415732] reg-fixed-voltage fixedregulator-evm_12v0: coherent_dma_mask ffffffff bus_dma_limit 0
[    0.425130] reg-fixed-voltage fixedregulator-evm_1v8: coherent_dma_mask ffffffff bus_dma_limit 0
[    0.434425] reg-fixed-voltage fixedregulator-sd: coherent_dma_mask ffffffff bus_dma_limit 0
[    0.443154] reg-fixed-voltage fixedregulator-evm_3v3_sw: coherent_dma_mask ffffffff bus_dma_limit 0
[    0.452704] reg-fixed-voltage fixedregulator-aic_dvdd: coherent_dma_mask ffffffff bus_dma_limit 0
[    0.462128] reg-fixed-voltage fixedregulator-evm3v3: coherent_dma_mask ffffffff bus_dma_limit 0
[    0.475522] reg-fixed-voltage fixedregulator-evm_5v0: coherent_dma_mask ffffffff bus_dma_limit 0
[    0.488967] reg-fixed-voltage fixedregulator-evm_3v6: coherent_dma_mask ffffffff bus_dma_limit 0
[    0.502370] reg-fixed-voltage fixedregulator-mmcwl: coherent_dma_mask ffffffff bus_dma_limit 0
[    0.511344] reg-fixed-voltage fixedregulator-vtt: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.126761] armv7-pmu pmu: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.205964] ti-sysc 4a002000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.216197] ti-dma-crossbar 4a002b78.dma-router: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.225136] ti-dma-crossbar 4a002c78.dma-router: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.233950] ti-sysc 4a005000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.243850] ti-sysc 4a008000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.255339] ti-sysc 4a056000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.264194] omap-dma-engine 4a056000.dma-controller: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.301417] ti-sysc 4a080000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.310052] omap-ocp2scp 4a080000.ocp2scp: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.319096] ti-sysc 4a090000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.327664] omap-ocp2scp 4a090000.ocp2scp: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.336484] ti-sysc 4a0d9038.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.344789] ti-sysc 4a0dd038.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.353077] ti-sysc 4a0f4000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.361397] ti-sysc 4a0f6000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.369973] ti-sysc 4ae06000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.381433] ti-sysc 4ae0c000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.389923] ti-sysc 4ae10000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.398621] omap_gpio 4ae10000.gpio: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.410819] ti-sysc 4ae14000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.420131] ti-sysc 4ae20000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.428888] ti-sysc 4ae2b050.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.437346] ti-sysc 4ae3c020.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.445970] ti-sysc 48020050.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.454620] ti-sysc 48032000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.463231] ti-sysc 48034000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.471827] ti-sysc 48036000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.480417] ti-sysc 4803e000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.489001] ti-sysc 48051000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.497542] omap_gpio 48051000.gpio: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.505504] ti-sysc 48053000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.514201] omap_gpio 48053000.gpio: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.522119] ti-sysc 48055000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.530792] omap_gpio 48055000.gpio: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.538700] ti-sysc 48057000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.547362] omap_gpio 48057000.gpio: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.555278] ti-sysc 48059000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.563950] omap_gpio 48059000.gpio: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.571856] ti-sysc 4805b000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.580533] omap_gpio 4805b000.gpio: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.588444] ti-sysc 4805d000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.597098] omap_gpio 4805d000.gpio: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.605010] ti-sysc 48060000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.613570] omap_i2c 48060000.i2c: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.627029] ti-sysc 48066050.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.635352] ti-sysc 48068050.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.643693] ti-sysc 4806a050.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.652326] ti-sysc 4806c050.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.660962] ti-sysc 4806e050.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.669281] ti-sysc 48070000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.677833] omap_i2c 48070000.i2c: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.723570] palmas-pmic 48070000.i2c:tps659038@58:tps659038_pmic: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.852826] ti-sysc 48072000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.861432] omap_i2c 48072000.i2c: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.913194] ti-sysc 48078000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.921817] ti-sysc 4807a000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.930136] ti-sysc 4807c000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.938463] ti-sysc 48086000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.947040] ti-sysc 48088000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.955640] ti-sysc 48091fe0.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.964262] ti-sysc 48098000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.972874] ti-sysc 4809a000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.981478] ti-sysc 4809c000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.990191] ti-sysc 480a5030.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    1.998831] ti-sysc 480ad000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.007126] ti-sysc 480b2000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.015732] ti-sysc 480b4000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.024397] ti-sysc 480b8000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.032706] ti-sysc 480ba000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.041016] ti-sysc 480d1000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.049674] ti-sysc 48420050.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.058001] ti-sysc 48422050.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.066302] ti-sysc 48424050.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.074617] ti-sysc 4843c000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.083140] ti-sysc 4843e000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.091459] ti-sysc 48440000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.099776] ti-sysc 48442000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.108088] ti-sysc 48460000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.116415] ti-sysc 48464000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.124742] ti-sysc 48468000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.133469] ti-sysc 4846c000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.141786] ti-sysc 48470000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.150105] ti-sysc 48474000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.158421] ti-sysc 48478000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.166719] ti-sysc 4847c000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.175035] ti-sysc 48480020.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.183342] ti-sysc 48485200.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.192236] ti-sysc 48802000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.200571] ti-sysc 48820000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.209169] ti-sysc 48822000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.217768] ti-sysc 48824000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.226640] ti-sysc 48826000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.235368] ti-sysc 48828000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.243989] ti-sysc 4882a000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.252585] ti-sysc 4882c000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.261176] ti-sysc 4882e000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.269762] ti-sysc 48838074.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.278672] ti-sysc 4883a000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.286972] ti-sysc 4883c000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.295283] ti-sysc 4883e000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.303599] ti-sysc 48840000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.312384] ti-sysc 48842000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.321164] ti-sysc 48844000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.329478] ti-sysc 48846000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.337787] ti-sysc 4885e000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.346085] ti-sysc 48860000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.354397] ti-sysc 48862000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.362704] ti-sysc 48864000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.371014] ti-sysc 48880000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.379707] ti-sysc 488c0000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.388368] ti-sysc 48900000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.396669] ti-sysc 48940000.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.404974] ti-sysc 489d0010.target-module: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.413835] ti-sysc 40d01000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    2.422743] ti-sysc 40d02000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    2.431628] ti-sysc 58882000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    2.440531] ti-sysc 55082000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    2.449459] ti-sysc 5600fe00.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    2.458381] ti-sysc 4b500080.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    2.467554] ti-sysc 4b700080.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    2.476728] ti-sysc 4b101100.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    2.485905] ti-sysc 41501000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    2.494817] ti-sysc 41502000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    2.504711] ti-pipe3 4a084400.phy: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.512311] ti-pipe3 4a094000.pciephy: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.520403] ti-pipe3 4a096000.phy: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.528429] phy-gmii-sel 4a002554.phy-gmii-sel: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.537864] pinctrl-single 4a003400.pinmux: coherent_dma_mask ffffffff bus_dma_limit 0
[    2.553170] ti-iodelay 4844a000.padconf: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    2.562873] dra7-pcie 51000000.pcie: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.702194] dra7-atl 4843c000.atl: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.710396] omap_prm 4ae06400.prm: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.717831] omap_prm 4ae06500.prm: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.725243] omap_prm 4ae06700.prm: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.732669] omap_prm 4ae06f00.prm: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.740097] omap_prm 4ae07b00.prm: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.747507] omap_prm 4ae07b40.prm: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.754931] omap_prm 4ae07b80.prm: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.762354] omap_prm 4ae07bc0.prm: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.769777] omap_prm 4ae07c00.prm: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.778520] pbias-regulator 4a002e00.pbias_regulator: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.801322] ti_abb 4ae07ddc.regulator-abb-mpu: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    3.810628] ti_abb 4ae07e34.regulator-abb-ivahd: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    3.820099] ti_abb 4ae07e30.regulator-abb-dspeve: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    3.829648] ti_abb 4ae07de4.regulator-abb-gpu: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    3.847872] omap8250 48020000.serial: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.865171] omap8250 4806a000.serial: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.900927] omap8250 4806c000.serial: coherent_dma_mask ffffffff bus_dma_limit 0
[    3.938464] ahci 4a140000.sata: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    4.014880] omap-elm 48078000.elm: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.022584] omap2_mcspi 48098000.spi: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.030387] omap2_mcspi 4809a000.spi: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.045347] cpsw 48484000.ethernet: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.053085] davinci_mdio 48485000.mdio: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.186373] ti-soc-thermal 4a0021e0.bandgap: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    4.197942] ti_opp_supply 4a003b20.opp-supply: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    4.234731] sdhci-omap 4809c000.mmc: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.257030] sdhci-omap 480b4000.mmc: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.298030] sdhci-omap 480d1000.mmc: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.319188] omap_timer 4ae20000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.326842] omap_timer 48032000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.334480] omap_timer 48034000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.342121] omap_timer 48036000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.355045] omap_timer 4803e000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.362722] omap_timer 48086000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.370359] omap_timer 48088000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.378020] omap_timer 48820000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.385638] omap_timer 48822000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.393338] omap_timer 48824000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.401054] omap_timer 48826000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.408682] omap_timer 48828000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.416299] omap_timer 4882a000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.423926] omap_timer 4882c000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.431564] omap_timer 4882e000.timer: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.542727] reg-fixed-voltage fixedregulator-sd: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.551676] reg-fixed-voltage fixedregulator-mmcwl: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.560659] reg-fixed-voltage fixedregulator-vtt: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.574085] ti-sysc 40d01000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    4.583356] omap-iommu 40d01000.mmu: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.596839] ti-sysc 40d02000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    4.605865] omap-iommu 40d02000.mmu: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.619137] ti-sysc 58882000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    4.650679] ti-sysc 55082000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    4.659729] omap-iommu 55082000.mmu: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.673050] ti-sysc 41501000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    4.682122] omap-iommu 41501000.mmu: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.695553] ti-sysc 41502000.target-module: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[    4.704553] omap-iommu 41502000.mmu: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.718193] sdhci-omap 4809c000.mmc: coherent_dma_mask ffffffff bus_dma_limit 0
[    4.794819] sdhci-omap 480d1000.mmc: coherent_dma_mask ffffffff bus_dma_limit 0
[    9.595632] omap_rng 48090000.rng: coherent_dma_mask ffffffff bus_dma_limit 0
[    9.816725] omap-des 480a5000.des: coherent_dma_mask ffffffff bus_dma_limit 0
[  OK  ] Listening on Avahi mDNS/DNS-SD Stack Activati[    9.884459] omap_hdq 480b2000.1w: coherent_dma_mask ffffffff bus_dma_limit 0
[   10.387555] davinci-mcasp 48468000.mcasp: coherent_dma_mask ffffffff bus_dma_limit 0
[   10.601762] omap_rtc 48838000.rtc: coherent_dma_mask ffffffff bus_dma_limit 0
[   10.690955] omap-mailbox 48840000.mailbox: coherent_dma_mask ffffffff bus_dma_limit 0
[   10.705329] omap-mailbox 48842000.mailbox: coherent_dma_mask ffffffff bus_dma_limit 0
[   10.944741] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask ffffffff bus_dma_limit 0
[   10.955211] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask ffffffff bus_dma_limit 0
[   11.363422] omap-usb2 4a084000.phy: coherent_dma_mask ffffffff bus_dma_limit 0
[   11.371219] omap-usb2 4a085000.phy: coherent_dma_mask ffffffff bus_dma_limit 0
[   11.379847] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask ffffffff bus_dma_limit 0
[   11.388227] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.168625] ti-qspi 4b300000.spi: coherent_dma_mask ffffffff bus_dma_limit ffffffff
[   12.191757] omap-sham 4b101000.sham: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.222185] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.230552] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.383690] omap-aes 4b500000.aes: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.515766] omap_wdt 4ae14000.wdt: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.577845] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.586136] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.637362] c_can_platform 4ae3c000.can: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.659521] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.668206] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.771243] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.779655] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.820295] extcon-usb-gpio extcon_usb1: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.841609] extcon-usb-gpio extcon_usb2: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.850013] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.866441] omap-aes 4b700000.aes: coherent_dma_mask ffffffff bus_dma_limit 0
[   12.880846] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask ffffffff bus_dma_limit 0
[   13.014297] gpio-keys gpio_keys: coherent_dma_mask ffffffff bus_dma_limit 0
[   13.033599] leds-gpio leds: coherent_dma_mask ffffffff bus_dma_limit 0
[   13.063978] asoc-simple-card sound0: coherent_dma_mask ffffffff bus_dma_limit 0
[   14.294633] dwc3 48890000.usb: coherent_dma_mask ffffffff bus_dma_limit 0
[   14.328563] dwc3 488d0000.usb: coherent_dma_mask ffffffff bus_dma_limit 0

Robin Murphy March 11, 2020, 12:25 p.m. UTC | #7

On 2020-03-11 10:28 am, Roger Quadros wrote:
> 
> 
> On 11/03/2020 09:13, Roger Quadros wrote:
>>
>>
>> On 10/03/2020 18:16, Robin Murphy wrote:
>>> On 10/03/2020 3:48 pm, Tony Lindgren wrote:
>>>> * Tero Kristo <t-kristo@ti.com> [200310 14:46]:
>>>>> On 10/03/2020 13:53, Roger Quadros wrote:
>>>>>> The L3 interconnect can access only 32-bits of address.
>>>>>> Add the dma-ranges property to reflect this limit.
>>>>>>
>>>>>> This will ensure that no device under L3 is
>>>>>> given > 32-bit address for DMA.
>>>>>>
>>>>>> Issue was observed only with SATA on DRA7-EVM with 4GB RAM
>>>>>> and CONFIG_ARM_LPAE enabled. This is because the controller
>>>>>> can perform 64-bit DMA and was setting the dma_mask to 64-bit.
>>>>>>
>>>>>> Setting the correct bus_dma_limit fixes the issue.
>>>>>
>>>>> This seems kind of messy to modify almost every DT node because of 
>>>>> this....
>>>>> Are you sure this is the only way to get it done? No way to modify 
>>>>> the sata
>>>>> node only which is impacted somehow?
>>>>>
>>>>> Also, what if you just pass 0xffffffff to the dma-ranges property? 
>>>>> That
>>>>> would avoid modifying every node I guess.
>>>>
>>>> Also, I think these interconnects are not limited to 32-bit access.
>>>> So yeah I too would prefer a top level dma-ranges property assuming
>>>> that works.
>>>>
>>>> I guess there dma-ranges should not be 0xffffffff though if
>>>> limited to 2GB :)
>>
>> Right, and the code expects it to not look like a mask.
>>  From of_dma_configure()
>>
>>          ret = of_dma_get_range(np, &dma_addr, &paddr, &size);
>>      ..
>>                  if (size & 1) {
>>                         dev_warn(dev, "Invalid size 0x%llx for 
>> dma-range\n",
>>                                   size);
>>                         size = size + 1;
>>                  }
>>
>>>
>>> It should work fine to just describe the Q3 and Q4 DDR regions as the 
>>> DMA range, i.e.:
>>>
>>>      ocp {
>>>          ...
>>>          dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
>>>          ...
>>>      };
>>>
>>> That would certainly be far less invasive :)
>>
>> This is brilliant! Thanks :)
>>
> 
> I noticed that all devices are not getting the right bus_dma_limit (see 
> kernel log at end).

Hmm, looks like those are all nodes with one or more intermediate levels 
between them and &ocp - if you have the bus_dma_mask -> bus_dma_limit 
change then presumably your kernel also contains 81db12ee15cb 
("of/address: Translate 'dma-ranges' for parent nodes missing 
'dma-ranges'")? I thought that was supposed to allow things like this to 
work without having to explicitly add "dma-ranges;" to all those 
intermediate nodes as well, but seemingly that isn't happening...

Enabling the debug prints from drivers/of/address.c should hopefully 
give enough to narrow down where and why of_dma_get_range() is giving up 
for these nodes (be warned there will be a *lot* of noise to sift through).

Robin.

> At least the following devices should be fixed right? Any other devices 
> I missed?
> 
> [    1.264194] omap-dma-engine 4a056000.dma-controller: 
> coherent_dma_mask ffffffff bus_dma_limit 0
> 
> [    4.583356] omap-iommu 40d01000.mmu: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.605865] omap-iommu 40d02000.mmu: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.659729] omap-iommu 55082000.mmu: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.682122] omap-iommu 41501000.mmu: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.704553] omap-iommu 41502000.mmu: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> 
> [    4.234731] sdhci-omap 4809c000.mmc: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.257030] sdhci-omap 480b4000.mmc: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.298030] sdhci-omap 480d1000.mmc: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    2.562873] dra7-pcie 51000000.pcie: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> 
> [   10.944741] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   10.955211] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> 
> cheers,
> -roger
> 
> 
> full list
> 
> [    0.286523] omap_l3_noc 44000000.ocp: coherent_dma_mask ffffffff 
> bus_dma_limit ffffffff
> [    0.323023] sram 40300000.ocmcram: coherent_dma_mask ffffffff 
> bus_dma_limit ffffffff
> [    0.365861] edma3-tptc 43400000.tptc: coherent_dma_mask ffffffff 
> bus_dma_limit ffffffff
> [    0.374205] edma3-tptc 43500000.tptc: coherent_dma_mask ffffffff 
> bus_dma_limit ffffffff
> [    0.382739] edma 43300000.edma: coherent_dma_mask ffffffff 
> bus_dma_limit ffffffff
> [    0.415732] reg-fixed-voltage fixedregulator-evm_12v0: 
> coherent_dma_mask ffffffff bus_dma_limit 0
> [    0.425130] reg-fixed-voltage fixedregulator-evm_1v8: 
> coherent_dma_mask ffffffff bus_dma_limit 0
> [    0.434425] reg-fixed-voltage fixedregulator-sd: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    0.443154] reg-fixed-voltage fixedregulator-evm_3v3_sw: 
> coherent_dma_mask ffffffff bus_dma_limit 0
> [    0.452704] reg-fixed-voltage fixedregulator-aic_dvdd: 
> coherent_dma_mask ffffffff bus_dma_limit 0
> [    0.462128] reg-fixed-voltage fixedregulator-evm3v3: 
> coherent_dma_mask ffffffff bus_dma_limit 0
> [    0.475522] reg-fixed-voltage fixedregulator-evm_5v0: 
> coherent_dma_mask ffffffff bus_dma_limit 0
> [    0.488967] reg-fixed-voltage fixedregulator-evm_3v6: 
> coherent_dma_mask ffffffff bus_dma_limit 0
> [    0.502370] reg-fixed-voltage fixedregulator-mmcwl: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    0.511344] reg-fixed-voltage fixedregulator-vtt: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.126761] armv7-pmu pmu: coherent_dma_mask ffffffff bus_dma_limit 0
> [    1.205964] ti-sysc 4a002000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.216197] ti-dma-crossbar 4a002b78.dma-router: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.225136] ti-dma-crossbar 4a002c78.dma-router: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.233950] ti-sysc 4a005000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.243850] ti-sysc 4a008000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.255339] ti-sysc 4a056000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.264194] omap-dma-engine 4a056000.dma-controller: 
> coherent_dma_mask ffffffff bus_dma_limit 0
> [    1.301417] ti-sysc 4a080000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.310052] omap-ocp2scp 4a080000.ocp2scp: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.319096] ti-sysc 4a090000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.327664] omap-ocp2scp 4a090000.ocp2scp: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.336484] ti-sysc 4a0d9038.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.344789] ti-sysc 4a0dd038.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.353077] ti-sysc 4a0f4000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.361397] ti-sysc 4a0f6000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.369973] ti-sysc 4ae06000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.381433] ti-sysc 4ae0c000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.389923] ti-sysc 4ae10000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.398621] omap_gpio 4ae10000.gpio: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.410819] ti-sysc 4ae14000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.420131] ti-sysc 4ae20000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.428888] ti-sysc 4ae2b050.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.437346] ti-sysc 4ae3c020.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.445970] ti-sysc 48020050.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.454620] ti-sysc 48032000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.463231] ti-sysc 48034000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.471827] ti-sysc 48036000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.480417] ti-sysc 4803e000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.489001] ti-sysc 48051000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.497542] omap_gpio 48051000.gpio: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.505504] ti-sysc 48053000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.514201] omap_gpio 48053000.gpio: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.522119] ti-sysc 48055000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.530792] omap_gpio 48055000.gpio: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.538700] ti-sysc 48057000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.547362] omap_gpio 48057000.gpio: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.555278] ti-sysc 48059000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.563950] omap_gpio 48059000.gpio: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.571856] ti-sysc 4805b000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.580533] omap_gpio 4805b000.gpio: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.588444] ti-sysc 4805d000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.597098] omap_gpio 4805d000.gpio: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.605010] ti-sysc 48060000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.613570] omap_i2c 48060000.i2c: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.627029] ti-sysc 48066050.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.635352] ti-sysc 48068050.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.643693] ti-sysc 4806a050.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.652326] ti-sysc 4806c050.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.660962] ti-sysc 4806e050.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.669281] ti-sysc 48070000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.677833] omap_i2c 48070000.i2c: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.723570] palmas-pmic 48070000.i2c:tps659038@58:tps659038_pmic: 
> coherent_dma_mask ffffffff bus_dma_limit 0
> [    1.852826] ti-sysc 48072000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.861432] omap_i2c 48072000.i2c: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    1.913194] ti-sysc 48078000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.921817] ti-sysc 4807a000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.930136] ti-sysc 4807c000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.938463] ti-sysc 48086000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.947040] ti-sysc 48088000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.955640] ti-sysc 48091fe0.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.964262] ti-sysc 48098000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.972874] ti-sysc 4809a000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.981478] ti-sysc 4809c000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.990191] ti-sysc 480a5030.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    1.998831] ti-sysc 480ad000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.007126] ti-sysc 480b2000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.015732] ti-sysc 480b4000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.024397] ti-sysc 480b8000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.032706] ti-sysc 480ba000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.041016] ti-sysc 480d1000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.049674] ti-sysc 48420050.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.058001] ti-sysc 48422050.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.066302] ti-sysc 48424050.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.074617] ti-sysc 4843c000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.083140] ti-sysc 4843e000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.091459] ti-sysc 48440000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.099776] ti-sysc 48442000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.108088] ti-sysc 48460000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.116415] ti-sysc 48464000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.124742] ti-sysc 48468000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.133469] ti-sysc 4846c000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.141786] ti-sysc 48470000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.150105] ti-sysc 48474000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.158421] ti-sysc 48478000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.166719] ti-sysc 4847c000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.175035] ti-sysc 48480020.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.183342] ti-sysc 48485200.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.192236] ti-sysc 48802000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.200571] ti-sysc 48820000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.209169] ti-sysc 48822000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.217768] ti-sysc 48824000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.226640] ti-sysc 48826000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.235368] ti-sysc 48828000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.243989] ti-sysc 4882a000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.252585] ti-sysc 4882c000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.261176] ti-sysc 4882e000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.269762] ti-sysc 48838074.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.278672] ti-sysc 4883a000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.286972] ti-sysc 4883c000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.295283] ti-sysc 4883e000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.303599] ti-sysc 48840000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.312384] ti-sysc 48842000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.321164] ti-sysc 48844000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.329478] ti-sysc 48846000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.337787] ti-sysc 4885e000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.346085] ti-sysc 48860000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.354397] ti-sysc 48862000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.362704] ti-sysc 48864000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.371014] ti-sysc 48880000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.379707] ti-sysc 488c0000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.388368] ti-sysc 48900000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.396669] ti-sysc 48940000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.404974] ti-sysc 489d0010.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.413835] ti-sysc 40d01000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    2.422743] ti-sysc 40d02000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    2.431628] ti-sysc 58882000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    2.440531] ti-sysc 55082000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    2.449459] ti-sysc 5600fe00.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    2.458381] ti-sysc 4b500080.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    2.467554] ti-sysc 4b700080.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    2.476728] ti-sysc 4b101100.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    2.485905] ti-sysc 41501000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    2.494817] ti-sysc 41502000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    2.504711] ti-pipe3 4a084400.phy: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    2.512311] ti-pipe3 4a094000.pciephy: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    2.520403] ti-pipe3 4a096000.phy: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    2.528429] phy-gmii-sel 4a002554.phy-gmii-sel: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.537864] pinctrl-single 4a003400.pinmux: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    2.553170] ti-iodelay 4844a000.padconf: coherent_dma_mask ffffffff 
> bus_dma_limit ffffffff
> [    2.562873] dra7-pcie 51000000.pcie: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.702194] dra7-atl 4843c000.atl: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.710396] omap_prm 4ae06400.prm: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.717831] omap_prm 4ae06500.prm: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.725243] omap_prm 4ae06700.prm: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.732669] omap_prm 4ae06f00.prm: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.740097] omap_prm 4ae07b00.prm: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.747507] omap_prm 4ae07b40.prm: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.754931] omap_prm 4ae07b80.prm: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.762354] omap_prm 4ae07bc0.prm: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.769777] omap_prm 4ae07c00.prm: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.778520] pbias-regulator 4a002e00.pbias_regulator: 
> coherent_dma_mask ffffffff bus_dma_limit 0
> [    3.801322] ti_abb 4ae07ddc.regulator-abb-mpu: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    3.810628] ti_abb 4ae07e34.regulator-abb-ivahd: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    3.820099] ti_abb 4ae07e30.regulator-abb-dspeve: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    3.829648] ti_abb 4ae07de4.regulator-abb-gpu: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    3.847872] omap8250 48020000.serial: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.865171] omap8250 4806a000.serial: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.900927] omap8250 4806c000.serial: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    3.938464] ahci 4a140000.sata: coherent_dma_mask ffffffff 
> bus_dma_limit ffffffff
> [    4.014880] omap-elm 48078000.elm: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.022584] omap2_mcspi 48098000.spi: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.030387] omap2_mcspi 4809a000.spi: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.045347] cpsw 48484000.ethernet: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.053085] davinci_mdio 48485000.mdio: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.186373] ti-soc-thermal 4a0021e0.bandgap: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    4.197942] ti_opp_supply 4a003b20.opp-supply: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    4.234731] sdhci-omap 4809c000.mmc: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.257030] sdhci-omap 480b4000.mmc: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.298030] sdhci-omap 480d1000.mmc: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.319188] omap_timer 4ae20000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.326842] omap_timer 48032000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.334480] omap_timer 48034000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.342121] omap_timer 48036000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.355045] omap_timer 4803e000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.362722] omap_timer 48086000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.370359] omap_timer 48088000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.378020] omap_timer 48820000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.385638] omap_timer 48822000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.393338] omap_timer 48824000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.401054] omap_timer 48826000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.408682] omap_timer 48828000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.416299] omap_timer 4882a000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.423926] omap_timer 4882c000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.431564] omap_timer 4882e000.timer: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.542727] reg-fixed-voltage fixedregulator-sd: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    4.551676] reg-fixed-voltage fixedregulator-mmcwl: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    4.560659] reg-fixed-voltage fixedregulator-vtt: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [    4.574085] ti-sysc 40d01000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    4.583356] omap-iommu 40d01000.mmu: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.596839] ti-sysc 40d02000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    4.605865] omap-iommu 40d02000.mmu: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.619137] ti-sysc 58882000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    4.650679] ti-sysc 55082000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    4.659729] omap-iommu 55082000.mmu: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.673050] ti-sysc 41501000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    4.682122] omap-iommu 41501000.mmu: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.695553] ti-sysc 41502000.target-module: coherent_dma_mask 
> ffffffff bus_dma_limit ffffffff
> [    4.704553] omap-iommu 41502000.mmu: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.718193] sdhci-omap 4809c000.mmc: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    4.794819] sdhci-omap 480d1000.mmc: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    9.595632] omap_rng 48090000.rng: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [    9.816725] omap-des 480a5000.des: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [  OK  ] Listening on Avahi mDNS/DNS-SD Stack Activati[    9.884459] 
> omap_hdq 480b2000.1w: coherent_dma_mask ffffffff bus_dma_limit 0
> [   10.387555] davinci-mcasp 48468000.mcasp: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   10.601762] omap_rtc 48838000.rtc: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   10.690955] omap-mailbox 48840000.mailbox: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   10.705329] omap-mailbox 48842000.mailbox: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   10.944741] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   10.955211] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   11.363422] omap-usb2 4a084000.phy: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   11.371219] omap-usb2 4a085000.phy: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   11.379847] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   11.388227] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   12.168625] ti-qspi 4b300000.spi: coherent_dma_mask ffffffff 
> bus_dma_limit ffffffff
> [   12.191757] omap-sham 4b101000.sham: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   12.222185] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   12.230552] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   12.383690] omap-aes 4b500000.aes: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   12.515766] omap_wdt 4ae14000.wdt: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   12.577845] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   12.586136] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   12.637362] c_can_platform 4ae3c000.can: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   12.659521] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   12.668206] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   12.771243] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   12.779655] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   12.820295] extcon-usb-gpio extcon_usb1: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   12.841609] extcon-usb-gpio extcon_usb2: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   12.850013] omap-dwc3 48880000.omap_dwc3_1: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   12.866441] omap-aes 4b700000.aes: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   12.880846] omap-dwc3 488c0000.omap_dwc3_2: coherent_dma_mask 
> ffffffff bus_dma_limit 0
> [   13.014297] gpio-keys gpio_keys: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   13.033599] leds-gpio leds: coherent_dma_mask ffffffff bus_dma_limit 0
> [   13.063978] asoc-simple-card sound0: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   14.294633] dwc3 48890000.usb: coherent_dma_mask ffffffff 
> bus_dma_limit 0
> [   14.328563] dwc3 488d0000.usb: coherent_dma_mask ffffffff 
> bus_dma_limit 0
>

Tony Lindgren March 11, 2020, 3:23 p.m. UTC | #8

* Roger Quadros <rogerq@ti.com> [200311 07:21]:
> 
> 
> On 10/03/2020 17:48, Tony Lindgren wrote:
> > * Tero Kristo <t-kristo@ti.com> [200310 14:46]:
> > > On 10/03/2020 13:53, Roger Quadros wrote:
> > > > The L3 interconnect can access only 32-bits of address.
> > > > Add the dma-ranges property to reflect this limit.
> > > > 
> > > > This will ensure that no device under L3 is
> > > > given > 32-bit address for DMA.
> > > > 
> > > > Issue was observed only with SATA on DRA7-EVM with 4GB RAM
> > > > and CONFIG_ARM_LPAE enabled. This is because the controller
> > > > can perform 64-bit DMA and was setting the dma_mask to 64-bit.
> > > > 
> > > > Setting the correct bus_dma_limit fixes the issue.
> > > 
> > > This seems kind of messy to modify almost every DT node because of this....
> > > Are you sure this is the only way to get it done? No way to modify the sata
> > > node only which is impacted somehow?
> > > 
> > > Also, what if you just pass 0xffffffff to the dma-ranges property? That
> > > would avoid modifying every node I guess.
> > 
> > Also, I think these interconnects are not limited to 32-bit access.
> 
> But from Table 2-1. L3_MAIN Memory Map
> 
> Start address	0x0000_0000
> End address	0xFFFF_FFFF
> 
> So it is 32-bit limit, right?

Hmm so what war Robin saying earlier that DMA access seems to be
limited to lower 2GB only though?

Regards,

Tony

Robin Murphy March 11, 2020, 3:47 p.m. UTC | #9

On 11/03/2020 3:23 pm, Tony Lindgren wrote:
> * Roger Quadros <rogerq@ti.com> [200311 07:21]:
>>
>>
>> On 10/03/2020 17:48, Tony Lindgren wrote:
>>> * Tero Kristo <t-kristo@ti.com> [200310 14:46]:
>>>> On 10/03/2020 13:53, Roger Quadros wrote:
>>>>> The L3 interconnect can access only 32-bits of address.
>>>>> Add the dma-ranges property to reflect this limit.
>>>>>
>>>>> This will ensure that no device under L3 is
>>>>> given > 32-bit address for DMA.
>>>>>
>>>>> Issue was observed only with SATA on DRA7-EVM with 4GB RAM
>>>>> and CONFIG_ARM_LPAE enabled. This is because the controller
>>>>> can perform 64-bit DMA and was setting the dma_mask to 64-bit.
>>>>>
>>>>> Setting the correct bus_dma_limit fixes the issue.
>>>>
>>>> This seems kind of messy to modify almost every DT node because of this....
>>>> Are you sure this is the only way to get it done? No way to modify the sata
>>>> node only which is impacted somehow?
>>>>
>>>> Also, what if you just pass 0xffffffff to the dma-ranges property? That
>>>> would avoid modifying every node I guess.
>>>
>>> Also, I think these interconnects are not limited to 32-bit access.
>>
>> But from Table 2-1. L3_MAIN Memory Map
>>
>> Start address	0x0000_0000
>> End address	0xFFFF_FFFF
>>
>> So it is 32-bit limit, right?
> 
> Hmm so what war Robin saying earlier that DMA access seems to be
> limited to lower 2GB only though?

That's the lower 2GB *of DRAM*, which occupies the upper 2GB of the L3 
memory map ;)

Robin.

Tony Lindgren March 11, 2020, 3:49 p.m. UTC | #10

* Robin Murphy <robin.murphy@arm.com> [200311 15:48]:
> On 11/03/2020 3:23 pm, Tony Lindgren wrote:
> > * Roger Quadros <rogerq@ti.com> [200311 07:21]:
> > > 
> > > 
> > > On 10/03/2020 17:48, Tony Lindgren wrote:
> > > > * Tero Kristo <t-kristo@ti.com> [200310 14:46]:
> > > > > On 10/03/2020 13:53, Roger Quadros wrote:
> > > > > > The L3 interconnect can access only 32-bits of address.
> > > > > > Add the dma-ranges property to reflect this limit.
> > > > > > 
> > > > > > This will ensure that no device under L3 is
> > > > > > given > 32-bit address for DMA.
> > > > > > 
> > > > > > Issue was observed only with SATA on DRA7-EVM with 4GB RAM
> > > > > > and CONFIG_ARM_LPAE enabled. This is because the controller
> > > > > > can perform 64-bit DMA and was setting the dma_mask to 64-bit.
> > > > > > 
> > > > > > Setting the correct bus_dma_limit fixes the issue.
> > > > > 
> > > > > This seems kind of messy to modify almost every DT node because of this....
> > > > > Are you sure this is the only way to get it done? No way to modify the sata
> > > > > node only which is impacted somehow?
> > > > > 
> > > > > Also, what if you just pass 0xffffffff to the dma-ranges property? That
> > > > > would avoid modifying every node I guess.
> > > > 
> > > > Also, I think these interconnects are not limited to 32-bit access.
> > > 
> > > But from Table 2-1. L3_MAIN Memory Map
> > > 
> > > Start address	0x0000_0000
> > > End address	0xFFFF_FFFF
> > > 
> > > So it is 32-bit limit, right?
> > 
> > Hmm so what war Robin saying earlier that DMA access seems to be
> > limited to lower 2GB only though?
> 
> That's the lower 2GB *of DRAM*, which occupies the upper 2GB of the L3
> memory map ;)

OK thanks for clarifying it.

Regards,

Tony

ARM: dts: dra7: Add bus_dma_limit for L3 bus

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