| Message ID | 20200227110605.22144-2-m.felsch@pengutronix.de (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 50f5b89a32ec69fa80601e575a99a062f0b4904e |
| Headers | show |
| Series | [1/2] ARM: dts: imx6: phycore-som: explicit disable pmic watchdog during suspend | expand |
On Thu, Feb 27, 2020 at 12:06:05PM +0100, Marco Felsch wrote: > The pmic is a mfd device and supports gpios. Those gpios are not routed > to the SoM baseboard pin header but they are connected to the i.MX6. We > need the GPIO's to configure the pmic to select between the > suspend/resume arm and soc voltages > > Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> > > arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) Not sure why this is here. I removed it and applied the patch. Shawn > > diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi > index 8b71bf33ba30..41ebe4599e43 100644 > --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi > +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi > @@ -88,7 +88,7 @@ > reg = <0x50>; > }; > > - pmic@58 { > + pmic: pmic@58 { > compatible = "dlg,da9062"; > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_pmic>; > @@ -96,6 +96,8 @@ > interrupt-parent = <&gpio1>; > interrupts = <2 IRQ_TYPE_LEVEL_LOW>; > interrupt-controller; > + gpio-controller; > + #gpio-cells = <2>; > > da9062_rtc: rtc { > compatible = "dlg,da9062-rtc"; > -- > 2.20.1 >
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi index 8b71bf33ba30..41ebe4599e43 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi @@ -88,7 +88,7 @@ reg = <0x50>; }; - pmic@58 { + pmic: pmic@58 { compatible = "dlg,da9062"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; @@ -96,6 +96,8 @@ interrupt-parent = <&gpio1>; interrupts = <2 IRQ_TYPE_LEVEL_LOW>; interrupt-controller; + gpio-controller; + #gpio-cells = <2>; da9062_rtc: rtc { compatible = "dlg,da9062-rtc";
The pmic is a mfd device and supports gpios. Those gpios are not routed to the SoM baseboard pin header but they are connected to the i.MX6. We need the GPIO's to configure the pmic to select between the suspend/resume arm and soc voltages Signed-off-by: Marco Felsch <m.felsch@pengutronix.de> arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)