| Message ID | 20200311071823.117899-2-jitao.shi@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | mt8183 dpi supports dual edge and pin mode swap | expand |
Hi, On 11/03/2020 08:18, Jitao Shi wrote: > Some chips's sample mode are rising, falling and dual edge (both > falling and rising edge). > Extern the pclk-sample property to support dual edge. > > Acked-by: Rob Herring <robh@kernel.org> > Reviewed-by: CK Hu <ck.hu@mediatek.com> > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > --- > Documentation/devicetree/bindings/media/video-interfaces.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt > index f884ada0bffc..da9ad24935db 100644 > --- a/Documentation/devicetree/bindings/media/video-interfaces.txt > +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt > @@ -118,8 +118,8 @@ Optional endpoint properties > - data-enable-active: similar to HSYNC and VSYNC, specifies the data enable > signal polarity. > - field-even-active: field signal level during the even field data transmission. > -- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock > - signal. > +- pclk-sample: sample data on rising (1), falling (0) or both rising and > + falling (2) edge of the pixel clock signal. > - sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for > LOW/HIGH respectively. > - data-lanes: an array of physical data lane indexes. Position of an entry > This changes the bus format, but we recently introduced a bus format negociation between bridges to avoid adding such properties into DT, and make bus format setup dynamic between an encoder and a bridge. It would be great to use that instead. Neil
Hi, Jitao: I agree with Neil, so please base on Boris' effort to negotiate with bridge. Regards, Chun-Kuang Hu Neil Armstrong <narmstrong@baylibre.com> 於 2020年3月11日 週三 下午9:53寫道： > > Hi, > > On 11/03/2020 08:18, Jitao Shi wrote: > > Some chips's sample mode are rising, falling and dual edge (both > > falling and rising edge). > > Extern the pclk-sample property to support dual edge. > > > > Acked-by: Rob Herring <robh@kernel.org> > > Reviewed-by: CK Hu <ck.hu@mediatek.com> > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > > --- > > Documentation/devicetree/bindings/media/video-interfaces.txt | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt > > index f884ada0bffc..da9ad24935db 100644 > > --- a/Documentation/devicetree/bindings/media/video-interfaces.txt > > +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt > > @@ -118,8 +118,8 @@ Optional endpoint properties > > - data-enable-active: similar to HSYNC and VSYNC, specifies the data enable > > signal polarity. > > - field-even-active: field signal level during the even field data transmission. > > -- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock > > - signal. > > +- pclk-sample: sample data on rising (1), falling (0) or both rising and > > + falling (2) edge of the pixel clock signal. > > - sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for > > LOW/HIGH respectively. > > - data-lanes: an array of physical data lane indexes. Position of an entry > > > > This changes the bus format, but we recently introduced a bus format negociation > between bridges to avoid adding such properties into DT, and make bus format setup > dynamic between an encoder and a bridge. > > It would be great to use that instead. > > Neil > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
diff --git a/Documentation/devicetree/bindings/media/video-interfaces.txt b/Documentation/devicetree/bindings/media/video-interfaces.txt index f884ada0bffc..da9ad24935db 100644 --- a/Documentation/devicetree/bindings/media/video-interfaces.txt +++ b/Documentation/devicetree/bindings/media/video-interfaces.txt @@ -118,8 +118,8 @@ Optional endpoint properties - data-enable-active: similar to HSYNC and VSYNC, specifies the data enable signal polarity. - field-even-active: field signal level during the even field data transmission. -- pclk-sample: sample data on rising (1) or falling (0) edge of the pixel clock - signal. +- pclk-sample: sample data on rising (1), falling (0) or both rising and + falling (2) edge of the pixel clock signal. - sync-on-green-active: active state of Sync-on-green (SoG) signal, 0/1 for LOW/HIGH respectively. - data-lanes: an array of physical data lane indexes. Position of an entry