| Message ID | 20200317150653.9008-1-zhiwei_liu@c-sky.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | target/riscv: support vector extension v0.7.1 | expand |
Patchew URL: https://patchew.org/QEMU/20200317150653.9008-1-zhiwei_liu@c-sky.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v6 00/61] target/riscv: support vector extension v0.7.1
Message-id: 20200317150653.9008-1-zhiwei_liu@c-sky.com
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Switched to a new branch 'test'
2e4bde1 target/riscv: configure and turn on vector extension from command line
4b36c5b target/riscv: vector compress instruction
67f4b44 target/riscv: vector register gather instruction
49f07c3 target/riscv: vector slide instructions
4139f53 target/riscv: floating-point scalar move instructions
9054c76 target/riscv: integer scalar move instruction
ba5456b target/riscv: integer extract instruction
5ee6b5a target/riscv: vector element index instruction
0bdafdc target/riscv: vector iota instruction
ee6d643 target/riscv: set-X-first mask bit
4ead442 target/riscv: vmfirst find-first-set mask bit
ec60662 target/riscv: vector mask population count vmpopc
b8ce0ac target/riscv: vector mask-register logical instructions
7beabd9 target/riscv: vector widening floating-point reduction instructions
1a18665 target/riscv: vector single-width floating-point reduction instructions
565439d target/riscv: vector wideing integer reduction instructions
82df77f target/riscv: vector single-width integer reduction instructions
f7e55c3 target/riscv: narrowing floating-point/integer type-convert instructions
4ac4ded target/riscv: widening floating-point/integer type-convert instructions
2f11992 target/riscv: vector floating-point/integer type-convert instructions
477eace target/riscv: vector floating-point merge instructions
0732540 target/riscv: vector floating-point classify instructions
19d2d5a target/riscv: vector floating-point compare instructions
d4d43fb target/riscv: vector floating-point sign-injection instructions
9ef556b target/riscv: vector floating-point min/max instructions
571725a target/riscv: vector floating-point square-root instruction
08494ab target/riscv: vector widening floating-point fused multiply-add instructions
ab50bf7 target/riscv: vector single-width floating-point fused multiply-add instructions
dc34bf8 target/riscv: vector widening floating-point multiply
3fc17ef target/riscv: vector single-width floating-point multiply/divide instructions
d67acb2 target/riscv: vector widening floating-point add/subtract instructions
c0e1ffb target/riscv: vector single-width floating-point add/subtract instructions
890ffc8 target/riscv: vector narrowing fixed-point clip instructions
97d0668 target/riscv: vector single-width scaling shift instructions
bc83728 target/riscv: vector widening saturating scaled multiply-add
9dff733 target/riscv: vector single-width fractional multiply with rounding and saturation
5ec9bf2 target/riscv: vector single-width averaging add and subtract
c282006 target/riscv: vector single-width saturating add and subtract
554de44 target/riscv: vector integer merge and move instructions
07d039c target/riscv: vector widening integer multiply-add instructions
4c6508e target/riscv: vector single-width integer multiply-add instructions
9f51ead target/riscv: vector widening integer multiply instructions
0e73109 target/riscv: vector integer divide instructions
fbdc194 target/riscv: vector single-width integer multiply instructions
3286d40 target/riscv: vector integer min/max instructions
28536d1 target/riscv: vector integer comparison instructions
ce050ba target/riscv: vector narrowing integer right shift instructions
7fb5aec target/riscv: vector single-width bit shift instructions
47904d5 target/riscv: vector bitwise logical instructions
4a73a38 target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
2e751a7 target/riscv: vector widening integer add and subtract
5e0b94f target/riscv: vector single-width integer add and subtract
3c57c83 target/riscv: add vector amo operations
e9d6c14 target/riscv: add fault-only-first unit stride load
3bbd6b7 target/riscv: add vector index load and store instructions
9e091e5 target/riscv: add vector stride load and store instructions
52e1baf target/riscv: add an internals.h header
26d5739 target/riscv: add vector configure instruction
c73587c target/riscv: support vector extension csr
3958fdc target/riscv: implementation-defined constant parameters
04b872f target/riscv: add vector extension field in CPURISCVState
=== OUTPUT BEGIN ===
1/61 Checking commit 04b872faf753 (target/riscv: add vector extension field in CPURISCVState)
2/61 Checking commit 3958fdc5ce52 (target/riscv: implementation-defined constant parameters)
3/61 Checking commit c73587c5bac5 (target/riscv: support vector extension csr)
4/61 Checking commit 26d5739da671 (target/riscv: add vector configure instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#160:
new file mode 100644
total: 0 errors, 1 warnings, 284 lines checked
Patch 4/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/61 Checking commit 52e1baf3c638 (target/riscv: add an internals.h header)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#14:
new file mode 100644
total: 0 errors, 1 warnings, 24 lines checked
Patch 5/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/61 Checking commit 9e091e5cb15e (target/riscv: add vector stride load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#273: FILE: target/riscv/insn_trans/trans_rvv.inc.c:133:
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
^
ERROR: spaces required around that '*' (ctx:WxV)
#821: FILE: target/riscv/vector_helper.c:256:
+ vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
^
ERROR: spaces required around that '*' (ctx:WxV)
#821: FILE: target/riscv/vector_helper.c:256:
+ vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
^
ERROR: spaces required around that '*' (ctx:WxV)
#921: FILE: target/riscv/vector_helper.c:356:
+ vext_ldst_elem_fn *ldst_elem,
^
ERROR: spaces required around that '*' (ctx:WxV)
#922: FILE: target/riscv/vector_helper.c:357:
+ clear_fn *clear_elem,
^
total: 5 errors, 0 warnings, 969 lines checked
Patch 6/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/61 Checking commit 3bbd6b7b0cfd (target/riscv: add vector index load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#245: FILE: target/riscv/vector_helper.c:482:
+ vext_ldst_elem_fn *ldst_elem,
^
ERROR: spaces required around that '*' (ctx:WxV)
#246: FILE: target/riscv/vector_helper.c:483:
+ clear_fn *clear_elem,
^
total: 2 errors, 0 warnings, 304 lines checked
Patch 7/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/61 Checking commit e9d6c14e8ef0 (target/riscv: add fault-only-first unit stride load)
ERROR: spaces required around that '*' (ctx:WxV)
#156: FILE: target/riscv/vector_helper.c:583:
+ vext_ldst_elem_fn *ldst_elem,
^
ERROR: spaces required around that '*' (ctx:WxV)
#157: FILE: target/riscv/vector_helper.c:584:
+ clear_fn *clear_elem,
^
total: 2 errors, 0 warnings, 223 lines checked
Patch 8/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/61 Checking commit 3c57c83095dc (target/riscv: add vector amo operations)
ERROR: spaces required around that '*' (ctx:WxV)
#356: FILE: target/riscv/vector_helper.c:764:
+ vext_amo_noatomic_fn *noatomic_op,
^
ERROR: spaces required around that '*' (ctx:WxV)
#357: FILE: target/riscv/vector_helper.c:765:
+ clear_fn *clear_elem,
^
total: 2 errors, 0 warnings, 374 lines checked
Patch 9/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/61 Checking commit 5e0b94fb1267 (target/riscv: vector single-width integer add and subtract)
ERROR: spaces required around that '*' (ctx:WxV)
#87: FILE: target/riscv/insn_trans/trans_rvv.inc.c:749:
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
^
ERROR: spaces required around that '*' (ctx:WxV)
#379: FILE: target/riscv/vector_helper.c:869:
+ opivv2_fn *fn, clear_fn *clearfn)
^
ERROR: spaces required around that '*' (ctx:WxV)
#379: FILE: target/riscv/vector_helper.c:869:
+ opivv2_fn *fn, clear_fn *clearfn)
^
ERROR: spaces required around that '*' (ctx:WxV)
#447: FILE: target/riscv/vector_helper.c:937:
+ opivx2_fn fn, clear_fn *clearfn)
^
total: 4 errors, 0 warnings, 457 lines checked
Patch 10/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/61 Checking commit 2e751a721905 (target/riscv: vector widening integer add and subtract)
12/61 Checking commit 4a73a38600a4 (target/riscv: vector integer add-with-carry / subtract-with-borrow instructions)
13/61 Checking commit 47904d522b9c (target/riscv: vector bitwise logical instructions)
14/61 Checking commit 7fb5aec01d02 (target/riscv: vector single-width bit shift instructions)
15/61 Checking commit ce050ba4e9a9 (target/riscv: vector narrowing integer right shift instructions)
16/61 Checking commit 28536d19e5b3 (target/riscv: vector integer comparison instructions)
17/61 Checking commit 3286d4006bfc (target/riscv: vector integer min/max instructions)
18/61 Checking commit fbdc194ba0c1 (target/riscv: vector single-width integer multiply instructions)
19/61 Checking commit 0e7310952ff1 (target/riscv: vector integer divide instructions)
20/61 Checking commit 9f51ead7c9b8 (target/riscv: vector widening integer multiply instructions)
21/61 Checking commit 4c6508eddc1d (target/riscv: vector single-width integer multiply-add instructions)
22/61 Checking commit 07d039c06cf0 (target/riscv: vector widening integer multiply-add instructions)
23/61 Checking commit 554de4474c91 (target/riscv: vector integer merge and move instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#70: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1504:
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
^
total: 1 errors, 0 warnings, 266 lines checked
Patch 23/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
24/61 Checking commit c2820065163c (target/riscv: vector single-width saturating add and subtract)
25/61 Checking commit 5ec9bf214601 (target/riscv: vector single-width averaging add and subtract)
26/61 Checking commit 9dff73340a51 (target/riscv: vector single-width fractional multiply with rounding and saturation)
27/61 Checking commit bc8372843994 (target/riscv: vector widening saturating scaled multiply-add)
28/61 Checking commit 97d06685a75c (target/riscv: vector single-width scaling shift instructions)
29/61 Checking commit 890ffc8bdec6 (target/riscv: vector narrowing fixed-point clip instructions)
30/61 Checking commit c0e1ffb73a0b (target/riscv: vector single-width floating-point add/subtract instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#275: FILE: target/riscv/vector_helper.c:3248:
+static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
^
total: 1 errors, 0 warnings, 264 lines checked
Patch 30/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/61 Checking commit d67acb2fa1ed (target/riscv: vector widening floating-point add/subtract instructions)
32/61 Checking commit 3fc17ef67053 (target/riscv: vector single-width floating-point multiply/divide instructions)
33/61 Checking commit dc34bf8778ef (target/riscv: vector widening floating-point multiply)
34/61 Checking commit ab50bf7b5c76 (target/riscv: vector single-width floating-point fused multiply-add instructions)
35/61 Checking commit 08494ab4740c (target/riscv: vector widening floating-point fused multiply-add instructions)
36/61 Checking commit 571725a42464 (target/riscv: vector floating-point square-root instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#66: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1959:
+static bool opfv_check(DisasContext *s, arg_rmr *a)
^
ERROR: spaces required around that '*' (ctx:WxV)
#76: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1969:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
^
total: 2 errors, 0 warnings, 114 lines checked
Patch 36/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
37/61 Checking commit 9ef556bc9648 (target/riscv: vector floating-point min/max instructions)
38/61 Checking commit d4d43fb84e5c (target/riscv: vector floating-point sign-injection instructions)
39/61 Checking commit 19d2d5a18f73 (target/riscv: vector floating-point compare instructions)
40/61 Checking commit 0732540f6c64 (target/riscv: vector floating-point classify instructions)
41/61 Checking commit 477eace32dab (target/riscv: vector floating-point merge instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#47: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2043:
+static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
^
total: 1 errors, 0 warnings, 85 lines checked
Patch 41/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
42/61 Checking commit 2f11992f70ec (target/riscv: vector floating-point/integer type-convert instructions)
43/61 Checking commit 4ac4ded6cc60 (target/riscv: widening floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#61: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2086:
+static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
^
ERROR: spaces required around that '*' (ctx:WxV)
#73: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2098:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
^
total: 2 errors, 0 warnings, 115 lines checked
Patch 43/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
44/61 Checking commit f7e55c3914fc (target/riscv: narrowing floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#61: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2128:
+static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
^
ERROR: spaces required around that '*' (ctx:WxV)
#73: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2140:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
^
total: 2 errors, 0 warnings, 112 lines checked
Patch 44/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
45/61 Checking commit 82df77f865c9 (target/riscv: vector single-width integer reduction instructions)
46/61 Checking commit 565439dce504 (target/riscv: vector wideing integer reduction instructions)
47/61 Checking commit 1a18665272b7 (target/riscv: vector single-width floating-point reduction instructions)
48/61 Checking commit 7beabd90f24b (target/riscv: vector widening floating-point reduction instructions)
49/61 Checking commit b8ce0acbc88d (target/riscv: vector mask-register logical instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#61: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2198:
+static bool trans_##NAME(DisasContext *s, arg_r *a) \
^
total: 1 errors, 0 warnings, 101 lines checked
Patch 49/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
50/61 Checking commit ec60662127b2 (target/riscv: vector mask population count vmpopc)
ERROR: spaces required around that '*' (ctx:WxV)
#43: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2222:
+static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
^
total: 1 errors, 0 warnings, 70 lines checked
Patch 50/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
51/61 Checking commit 4ead44243ee6 (target/riscv: vmfirst find-first-set mask bit)
52/61 Checking commit ee6d643154ee (target/riscv: set-X-first mask bit)
53/61 Checking commit 0bdafdcb7a39 (target/riscv: vector iota instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#46: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2309:
+static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
^
total: 1 errors, 0 warnings, 74 lines checked
Patch 53/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
54/61 Checking commit 5ee6b5a86189 (target/riscv: vector element index instruction)
55/61 Checking commit ba5456b1a0ee (target/riscv: integer extract instruction)
56/61 Checking commit 9054c7675709 (target/riscv: integer scalar move instruction)
57/61 Checking commit 4139f538725a (target/riscv: floating-point scalar move instructions)
58/61 Checking commit 49f07c39bbee (target/riscv: vector slide instructions)
59/61 Checking commit 67f4b4421131 (target/riscv: vector register gather instruction)
60/61 Checking commit 4b36c5b746a3 (target/riscv: vector compress instruction)
61/61 Checking commit 2e4bde112233 (target/riscv: configure and turn on vector extension from command line)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20200317150653.9008-1-zhiwei_liu@c-sky.com/testing.checkpatch/?type=message.
---
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Please send your feedback to patchew-devel@redhat.com
This patchset implements the vector extension for RISC-V on QEMU. You can also find the patchset and all *test cases* in my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v3). All the test cases are in the directory qemu/tests/riscv/vector/. They are riscv64 linux user mode programs. You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh. Features: * support specification riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/) * support basic vector extension. * support Zvlsseg. * support Zvamo. * not support Zvediv as it is changing. * SLEN always equals VLEN. * element width support 8bit, 16bit, 32bit, 64bit. Changelog: v6 * use gvec_dup Gvec IR to accellerate move and merge. * a better way to implement fixed point instructions. * a global check when vl == 0. * limit some macros to only one inline function call. * fixup sew error when use Gvec IR. * fixup bugs for corner cases. v5 * fixup a bug in tb flags. v4 * no change v3 * move check code from execution-time to translation-time * use a continous memory block for vector register description. * vector registers as direct fields in RISCVCPUState. * support VLEN configure from qemu command line. * support ELEN configure from qemu command line. * support vector specification version configure from qemu command line. * probe pages before real load or store access. * use probe_page_check for no-fault operations in linux user mode. * generation atomic exit exception when in parallel environment. * fixup a lot of concrete bugs. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (61): target/riscv: add vector extension field in CPURISCVState target/riscv: implementation-defined constant parameters target/riscv: support vector extension csr target/riscv: add vector configure instruction target/riscv: add an internals.h header target/riscv: add vector stride load and store instructions target/riscv: add vector index load and store instructions target/riscv: add fault-only-first unit stride load target/riscv: add vector amo operations target/riscv: vector single-width integer add and subtract target/riscv: vector widening integer add and subtract target/riscv: vector integer add-with-carry / subtract-with-borrow instructions target/riscv: vector bitwise logical instructions target/riscv: vector single-width bit shift instructions target/riscv: vector narrowing integer right shift instructions target/riscv: vector integer comparison instructions target/riscv: vector integer min/max instructions target/riscv: vector single-width integer multiply instructions target/riscv: vector integer divide instructions target/riscv: vector widening integer multiply instructions target/riscv: vector single-width integer multiply-add instructions target/riscv: vector widening integer multiply-add instructions target/riscv: vector integer merge and move instructions target/riscv: vector single-width saturating add and subtract target/riscv: vector single-width averaging add and subtract target/riscv: vector single-width fractional multiply with rounding and saturation target/riscv: vector widening saturating scaled multiply-add target/riscv: vector single-width scaling shift instructions target/riscv: vector narrowing fixed-point clip instructions target/riscv: vector single-width floating-point add/subtract instructions target/riscv: vector widening floating-point add/subtract instructions target/riscv: vector single-width floating-point multiply/divide instructions target/riscv: vector widening floating-point multiply target/riscv: vector single-width floating-point fused multiply-add instructions target/riscv: vector widening floating-point fused multiply-add instructions target/riscv: vector floating-point square-root instruction target/riscv: vector floating-point min/max instructions target/riscv: vector floating-point sign-injection instructions target/riscv: vector floating-point compare instructions target/riscv: vector floating-point classify instructions target/riscv: vector floating-point merge instructions target/riscv: vector floating-point/integer type-convert instructions target/riscv: widening floating-point/integer type-convert instructions target/riscv: narrowing floating-point/integer type-convert instructions target/riscv: vector single-width integer reduction instructions target/riscv: vector wideing integer reduction instructions target/riscv: vector single-width floating-point reduction instructions target/riscv: vector widening floating-point reduction instructions target/riscv: vector mask-register logical instructions target/riscv: vector mask population count vmpopc target/riscv: vmfirst find-first-set mask bit target/riscv: set-X-first mask bit target/riscv: vector iota instruction target/riscv: vector element index instruction target/riscv: integer extract instruction target/riscv: integer scalar move instruction target/riscv: floating-point scalar move instructions target/riscv: vector slide instructions target/riscv: vector register gather instruction target/riscv: vector compress instruction target/riscv: configure and turn on vector extension from command line target/riscv/Makefile.objs | 2 +- target/riscv/cpu.c | 49 + target/riscv/cpu.h | 82 +- target/riscv/cpu_bits.h | 15 + target/riscv/csr.c | 75 +- target/riscv/fpu_helper.c | 33 +- target/riscv/helper.h | 1073 +++++ target/riscv/insn32-64.decode | 11 + target/riscv/insn32.decode | 372 ++ target/riscv/insn_trans/trans_rvv.inc.c | 2710 +++++++++++++ target/riscv/internals.h | 35 + target/riscv/translate.c | 24 +- target/riscv/vector_helper.c | 4928 +++++++++++++++++++++++ 13 files changed, 9366 insertions(+), 43 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c create mode 100644 target/riscv/internals.h create mode 100644 target/riscv/vector_helper.c