| Message ID | 20200304203330.4967-6-maz@kernel.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | irqchip/gic-v4: GICv4.1 architecture support | expand |
On 2020/3/5 4:33, Marc Zyngier wrote: > The GICv4.1 spec says that it is CONTRAINED UNPREDICTABLE to write to s/CONTRAINED/CONSTRAINED/ > any of the GICR_INV{LPI,ALL}R registers if GICR_SYNCR.Busy == 1. > > To deal with it, we must ensure that only a single invalidation can > happen at a time for a given redistributor. Add a per-RD lock to that > effect and take it around the invalidation/syncr-read to deal with this. > > Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Thanks > --- > drivers/irqchip/irq-gic-v3-its.c | 6 ++++++ > drivers/irqchip/irq-gic-v3.c | 1 + > include/linux/irqchip/arm-gic-v3.h | 1 + > 3 files changed, 8 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c > index c84370245bea..fc5788584df7 100644 > --- a/drivers/irqchip/irq-gic-v3-its.c > +++ b/drivers/irqchip/irq-gic-v3-its.c > @@ -1373,10 +1373,12 @@ static void direct_lpi_inv(struct irq_data *d) > > /* Target the redistributor this LPI is currently routed to */ > cpu = irq_to_cpuid_lock(d, &flags); > + raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); > rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; > gic_write_lpir(val, rdbase + GICR_INVLPIR); > > wait_for_syncr(rdbase); > + raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); > irq_to_cpuid_unlock(d, flags); > } > > @@ -3662,9 +3664,11 @@ static void its_vpe_send_inv(struct irq_data *d) > void __iomem *rdbase; > > /* Target the redistributor this VPE is currently known on */ > + raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); > rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; > gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR); > wait_for_syncr(rdbase); > + raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); > } else { > its_vpe_send_cmd(vpe, its_send_inv); > } > @@ -3825,10 +3829,12 @@ static void its_vpe_4_1_invall(struct its_vpe *vpe) > val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id); > > /* Target the redistributor this vPE is currently known on */ > + raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); > rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; > gic_write_lpir(val, rdbase + GICR_INVALLR); > > wait_for_syncr(rdbase); > + raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); > } > > static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 73e87e176d76..ba405becab53 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -835,6 +835,7 @@ static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) > typer = gic_read_typer(ptr + GICR_TYPER); > if ((typer >> 32) == aff) { > u64 offset = ptr - region->redist_base; > + raw_spin_lock_init(&gic_data_rdist()->rd_lock); > gic_data_rdist_rd_base() = ptr; > gic_data_rdist()->phys_base = region->phys_base + offset; > > diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h > index c29a02678a6f..b28acfa71f82 100644 > --- a/include/linux/irqchip/arm-gic-v3.h > +++ b/include/linux/irqchip/arm-gic-v3.h > @@ -652,6 +652,7 @@ > > struct rdists { > struct { > + raw_spinlock_t rd_lock; > void __iomem *rd_base; > struct page *pend_page; > phys_addr_t phys_base; >
Hi, On 3/4/20 9:33 PM, Marc Zyngier wrote: > The GICv4.1 spec says that it is CONTRAINED UNPREDICTABLE to write to > any of the GICR_INV{LPI,ALL}R registers if GICR_SYNCR.Busy == 1. > > To deal with it, we must ensure that only a single invalidation can > happen at a time for a given redistributor. Add a per-RD lock to that > effect and take it around the invalidation/syncr-read to deal with this. > > Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Eric > --- > drivers/irqchip/irq-gic-v3-its.c | 6 ++++++ > drivers/irqchip/irq-gic-v3.c | 1 + > include/linux/irqchip/arm-gic-v3.h | 1 + > 3 files changed, 8 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c > index c84370245bea..fc5788584df7 100644 > --- a/drivers/irqchip/irq-gic-v3-its.c > +++ b/drivers/irqchip/irq-gic-v3-its.c > @@ -1373,10 +1373,12 @@ static void direct_lpi_inv(struct irq_data *d) > > /* Target the redistributor this LPI is currently routed to */ > cpu = irq_to_cpuid_lock(d, &flags); > + raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); > rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; > gic_write_lpir(val, rdbase + GICR_INVLPIR); > > wait_for_syncr(rdbase); > + raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); > irq_to_cpuid_unlock(d, flags); > } > > @@ -3662,9 +3664,11 @@ static void its_vpe_send_inv(struct irq_data *d) > void __iomem *rdbase; > > /* Target the redistributor this VPE is currently known on */ > + raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); > rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; > gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR); > wait_for_syncr(rdbase); > + raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); > } else { > its_vpe_send_cmd(vpe, its_send_inv); > } > @@ -3825,10 +3829,12 @@ static void its_vpe_4_1_invall(struct its_vpe *vpe) > val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id); > > /* Target the redistributor this vPE is currently known on */ > + raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); > rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; > gic_write_lpir(val, rdbase + GICR_INVALLR); > > wait_for_syncr(rdbase); > + raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); > } > > static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 73e87e176d76..ba405becab53 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -835,6 +835,7 @@ static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) > typer = gic_read_typer(ptr + GICR_TYPER); > if ((typer >> 32) == aff) { > u64 offset = ptr - region->redist_base; > + raw_spin_lock_init(&gic_data_rdist()->rd_lock); > gic_data_rdist_rd_base() = ptr; > gic_data_rdist()->phys_base = region->phys_base + offset; > > diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h > index c29a02678a6f..b28acfa71f82 100644 > --- a/include/linux/irqchip/arm-gic-v3.h > +++ b/include/linux/irqchip/arm-gic-v3.h > @@ -652,6 +652,7 @@ > > struct rdists { > struct { > + raw_spinlock_t rd_lock; > void __iomem *rd_base; > struct page *pend_page; > phys_addr_t phys_base; >
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index c84370245bea..fc5788584df7 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -1373,10 +1373,12 @@ static void direct_lpi_inv(struct irq_data *d) /* Target the redistributor this LPI is currently routed to */ cpu = irq_to_cpuid_lock(d, &flags); + raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; gic_write_lpir(val, rdbase + GICR_INVLPIR); wait_for_syncr(rdbase); + raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); irq_to_cpuid_unlock(d, flags); } @@ -3662,9 +3664,11 @@ static void its_vpe_send_inv(struct irq_data *d) void __iomem *rdbase; /* Target the redistributor this VPE is currently known on */ + raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; gic_write_lpir(d->parent_data->hwirq, rdbase + GICR_INVLPIR); wait_for_syncr(rdbase); + raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); } else { its_vpe_send_cmd(vpe, its_send_inv); } @@ -3825,10 +3829,12 @@ static void its_vpe_4_1_invall(struct its_vpe *vpe) val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id); /* Target the redistributor this vPE is currently known on */ + raw_spin_lock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; gic_write_lpir(val, rdbase + GICR_INVALLR); wait_for_syncr(rdbase); + raw_spin_unlock(&gic_data_rdist_cpu(vpe->col_idx)->rd_lock); } static int its_vpe_4_1_set_vcpu_affinity(struct irq_data *d, void *vcpu_info) diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 73e87e176d76..ba405becab53 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -835,6 +835,7 @@ static int __gic_populate_rdist(struct redist_region *region, void __iomem *ptr) typer = gic_read_typer(ptr + GICR_TYPER); if ((typer >> 32) == aff) { u64 offset = ptr - region->redist_base; + raw_spin_lock_init(&gic_data_rdist()->rd_lock); gic_data_rdist_rd_base() = ptr; gic_data_rdist()->phys_base = region->phys_base + offset; diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h index c29a02678a6f..b28acfa71f82 100644 --- a/include/linux/irqchip/arm-gic-v3.h +++ b/include/linux/irqchip/arm-gic-v3.h @@ -652,6 +652,7 @@ struct rdists { struct { + raw_spinlock_t rd_lock; void __iomem *rd_base; struct page *pend_page; phys_addr_t phys_base;
The GICv4.1 spec says that it is CONTRAINED UNPREDICTABLE to write to any of the GICR_INV{LPI,ALL}R registers if GICR_SYNCR.Busy == 1. To deal with it, we must ensure that only a single invalidation can happen at a time for a given redistributor. Add a per-RD lock to that effect and take it around the invalidation/syncr-read to deal with this. Signed-off-by: Marc Zyngier <maz@kernel.org> --- drivers/irqchip/irq-gic-v3-its.c | 6 ++++++ drivers/irqchip/irq-gic-v3.c | 1 + include/linux/irqchip/arm-gic-v3.h | 1 + 3 files changed, 8 insertions(+)