| Message ID | 20200321133842.2408823-1-mans0n@gorani.run (mailing list archive) |
|---|---|
| State | Mainlined |
| Commit | 6a214a28132f19ace3d835a6d8f6422ec80ad200 |
| Headers | show |
| Series | irqchip/versatile-fpga: Apply clear-mask earlier | expand |
On 2020-03-21 13:38, Sungbo Eo wrote: > Clear its own IRQs before the parent IRQ get enabled, so that the > remaining IRQs do not accidentally interrupt the parent IRQ controller. > > This patch also fixes a reboot bug on OX820 SoC, where the remaining > rps-timer IRQ raises a GIC interrupt that is left pending. After that, > the rps-timer IRQ is cleared during driver initialization, and there's > no IRQ left in rps-irq when local_irq_enable() is called, which evokes > an error message "unexpected IRQ trap". > > Fixes: bdd272cbb97a ("irqchip: versatile FPGA: support cascaded > interrupts from DT") > Signed-off-by: Sungbo Eo <mans0n@gorani.run> > Cc: Neil Armstrong <narmstrong@baylibre.com> > Cc: Daniel Golle <daniel@makrotopia.org> > --- > drivers/irqchip/irq-versatile-fpga.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/irqchip/irq-versatile-fpga.c > b/drivers/irqchip/irq-versatile-fpga.c > index 70e2cfff8175..f1386733d3bc 100644 > --- a/drivers/irqchip/irq-versatile-fpga.c > +++ b/drivers/irqchip/irq-versatile-fpga.c > @@ -212,6 +212,9 @@ int __init fpga_irq_of_init(struct device_node > *node, > if (of_property_read_u32(node, "valid-mask", &valid_mask)) > valid_mask = 0; > > + writel(clear_mask, base + IRQ_ENABLE_CLEAR); > + writel(clear_mask, base + FIQ_ENABLE_CLEAR); > + > /* Some chips are cascaded from a parent IRQ */ > parent_irq = irq_of_parse_and_map(node, 0); > if (!parent_irq) { > @@ -221,9 +224,6 @@ int __init fpga_irq_of_init(struct device_node > *node, > > fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); > > - writel(clear_mask, base + IRQ_ENABLE_CLEAR); > - writel(clear_mask, base + FIQ_ENABLE_CLEAR); > - > /* > * On Versatile AB/PB, some secondary interrupts have a direct > * pass-thru to the primary controller for IRQs 20 and 22-31 which > need You're on a roll! ;-) Queued for 5.7. Thanks, M.
On Sat, Mar 21, 2020 at 2:40 PM Sungbo Eo <mans0n@gorani.run> wrote: > Clear its own IRQs before the parent IRQ get enabled, so that the > remaining IRQs do not accidentally interrupt the parent IRQ controller. > > This patch also fixes a reboot bug on OX820 SoC, where the remaining > rps-timer IRQ raises a GIC interrupt that is left pending. After that, > the rps-timer IRQ is cleared during driver initialization, and there's > no IRQ left in rps-irq when local_irq_enable() is called, which evokes > an error message "unexpected IRQ trap". > > Fixes: bdd272cbb97a ("irqchip: versatile FPGA: support cascaded interrupts from DT") > Signed-off-by: Sungbo Eo <mans0n@gorani.run> > Cc: Neil Armstrong <narmstrong@baylibre.com> > Cc: Daniel Golle <daniel@makrotopia.org> Good catch! Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Marc: Cc stable? Yours, Linus Walleij
On 2020-03-22 11:45, Linus Walleij wrote: > On Sat, Mar 21, 2020 at 2:40 PM Sungbo Eo <mans0n@gorani.run> wrote: > >> Clear its own IRQs before the parent IRQ get enabled, so that the >> remaining IRQs do not accidentally interrupt the parent IRQ >> controller. >> >> This patch also fixes a reboot bug on OX820 SoC, where the remaining >> rps-timer IRQ raises a GIC interrupt that is left pending. After that, >> the rps-timer IRQ is cleared during driver initialization, and there's >> no IRQ left in rps-irq when local_irq_enable() is called, which evokes >> an error message "unexpected IRQ trap". >> >> Fixes: bdd272cbb97a ("irqchip: versatile FPGA: support cascaded >> interrupts from DT") >> Signed-off-by: Sungbo Eo <mans0n@gorani.run> >> Cc: Neil Armstrong <narmstrong@baylibre.com> >> Cc: Daniel Golle <daniel@makrotopia.org> > > Good catch! > Reviewed-by: Linus Walleij <linus.walleij@linaro.org> > > Marc: Cc stable? Sure, I'll add that. Thanks, M.
diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c index 70e2cfff8175..f1386733d3bc 100644 --- a/drivers/irqchip/irq-versatile-fpga.c +++ b/drivers/irqchip/irq-versatile-fpga.c @@ -212,6 +212,9 @@ int __init fpga_irq_of_init(struct device_node *node, if (of_property_read_u32(node, "valid-mask", &valid_mask)) valid_mask = 0; + writel(clear_mask, base + IRQ_ENABLE_CLEAR); + writel(clear_mask, base + FIQ_ENABLE_CLEAR); + /* Some chips are cascaded from a parent IRQ */ parent_irq = irq_of_parse_and_map(node, 0); if (!parent_irq) { @@ -221,9 +224,6 @@ int __init fpga_irq_of_init(struct device_node *node, fpga_irq_init(base, node->name, 0, parent_irq, valid_mask, node); - writel(clear_mask, base + IRQ_ENABLE_CLEAR); - writel(clear_mask, base + FIQ_ENABLE_CLEAR); - /* * On Versatile AB/PB, some secondary interrupts have a direct * pass-thru to the primary controller for IRQs 20 and 22-31 which need
Clear its own IRQs before the parent IRQ get enabled, so that the remaining IRQs do not accidentally interrupt the parent IRQ controller. This patch also fixes a reboot bug on OX820 SoC, where the remaining rps-timer IRQ raises a GIC interrupt that is left pending. After that, the rps-timer IRQ is cleared during driver initialization, and there's no IRQ left in rps-irq when local_irq_enable() is called, which evokes an error message "unexpected IRQ trap". Fixes: bdd272cbb97a ("irqchip: versatile FPGA: support cascaded interrupts from DT") Signed-off-by: Sungbo Eo <mans0n@gorani.run> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Daniel Golle <daniel@makrotopia.org> --- drivers/irqchip/irq-versatile-fpga.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)