| Message ID | 20200327061110.17371-2-vipin.anand@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Enable HDR on Gen9 devices with lspcon hdr capability | expand |
On 2020-03-27 at 11:41:04 +0530, Vipin Anand wrote: > From: Uma Shankar <uma.shankar@intel.com> > > LSPCON firmware exposes HDR capability through LPCON_CAPABILITIES > DPCD register. LSPCON implementations capable of supporting > HDR set HDR_CAPABILITY bit in LSPCON_CAPABILITIES to 1. This patch > reads the same, detects the HDR capability and adds this to > intel_lspcon struct. > > Signed-off-by: Uma Shankar <uma.shankar@intel.com> Hi Vipin , Looks like u forgot to add your sign-off. Thanks, Anshuman Gupta. > --- > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_lspcon.c | 32 +++++++++++++++++++ > 2 files changed, 33 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 888ea8a170d1..2f281da6d253 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1333,6 +1333,7 @@ struct intel_lspcon { > bool active; > enum drm_lspcon_mode mode; > enum lspcon_vendor vendor; > + bool hdr_supported; > }; > > struct intel_digital_port { > diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c > index d807c5648c87..2e41ae483a23 100644 > --- a/drivers/gpu/drm/i915/display/intel_lspcon.c > +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c > @@ -35,6 +35,8 @@ > #define LSPCON_VENDOR_PARADE_OUI 0x001CF8 > #define LSPCON_VENDOR_MCA_OUI 0x0060AD > > +#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 > + > /* AUX addresses to write MCA AVI IF */ > #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 > #define LSPCON_MCA_AVI_IF_CTRL 0x5DF > @@ -104,6 +106,31 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon) > return true; > } > > +static bool lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) > +{ > + struct intel_dp *dp = lspcon_to_intel_dp(lspcon); > + u8 hdr_caps; > + int ret; > + > + /* Enable HDR for MCA based LSPCON devices */ > + if (lspcon->vendor == LSPCON_VENDOR_MCA) > + ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS, > + &hdr_caps, 1); > + else > + return false; > + > + if (ret < 0) { > + DRM_DEBUG_KMS("hdr capability detection failed\n"); > + lspcon->hdr_supported = false; > + return false; > + } else if (hdr_caps & 0x1) { > + DRM_DEBUG_KMS("lspcon capable of HDR\n"); > + lspcon->hdr_supported = true; > + } > + > + return true; > +} > + > static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) > { > enum drm_lspcon_mode current_mode; > @@ -581,6 +608,11 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) > return false; > } > > + if (!lspcon_detect_hdr_capability(lspcon)) { > + DRM_ERROR("LSPCON hdr detection failed\n"); > + return false; > + } > + > connector->ycbcr_420_allowed = true; > lspcon->active = true; > DRM_DEBUG_KMS("Success: LSPCON init\n"); > -- > 2.26.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 888ea8a170d1..2f281da6d253 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1333,6 +1333,7 @@ struct intel_lspcon { bool active; enum drm_lspcon_mode mode; enum lspcon_vendor vendor; + bool hdr_supported; }; struct intel_digital_port { diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index d807c5648c87..2e41ae483a23 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -35,6 +35,8 @@ #define LSPCON_VENDOR_PARADE_OUI 0x001CF8 #define LSPCON_VENDOR_MCA_OUI 0x0060AD +#define DPCD_MCA_LSPCON_HDR_STATUS 0x70003 + /* AUX addresses to write MCA AVI IF */ #define LSPCON_MCA_AVI_IF_WRITE_OFFSET 0x5C0 #define LSPCON_MCA_AVI_IF_CTRL 0x5DF @@ -104,6 +106,31 @@ static bool lspcon_detect_vendor(struct intel_lspcon *lspcon) return true; } +static bool lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) +{ + struct intel_dp *dp = lspcon_to_intel_dp(lspcon); + u8 hdr_caps; + int ret; + + /* Enable HDR for MCA based LSPCON devices */ + if (lspcon->vendor == LSPCON_VENDOR_MCA) + ret = drm_dp_dpcd_read(&dp->aux, DPCD_MCA_LSPCON_HDR_STATUS, + &hdr_caps, 1); + else + return false; + + if (ret < 0) { + DRM_DEBUG_KMS("hdr capability detection failed\n"); + lspcon->hdr_supported = false; + return false; + } else if (hdr_caps & 0x1) { + DRM_DEBUG_KMS("lspcon capable of HDR\n"); + lspcon->hdr_supported = true; + } + + return true; +} + static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) { enum drm_lspcon_mode current_mode; @@ -581,6 +608,11 @@ bool lspcon_init(struct intel_digital_port *intel_dig_port) return false; } + if (!lspcon_detect_hdr_capability(lspcon)) { + DRM_ERROR("LSPCON hdr detection failed\n"); + return false; + } + connector->ycbcr_420_allowed = true; lspcon->active = true; DRM_DEBUG_KMS("Success: LSPCON init\n");