| Message ID | 20200127212319.1544222-3-robert.marko@sartura.hr (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v3,1/3] phy: add driver for Qualcomm IPQ40xx USB PHY | expand |
On Mon 27 Jan 13:23 PST 2020, Robert Marko wrote: > From: John Crispin <john@phrozen.org> > > Since we now have driver for the USB PHY, lets add the necessary nodes to DTSI. > > Signed-off-by: John Crispin <john@phrozen.org> > Tested-by: Robert Marko <robert.marko@sartura.hr> > Cc: Luka Perkov <luka.perkov@sartura.hr> Robert, I'm missing your Signed-off-by here (and I would like Kishon to take the PHY before merging this). Regards, Bjorn > --- > arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 +++++ > arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++ > 2 files changed, 94 insertions(+) > > diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi > index 418f9a022336..2ee5f05d5a43 100644 > --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi > +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi > @@ -109,5 +109,25 @@ > wifi@a800000 { > status = "ok"; > }; > + > + usb3_ss_phy: ssphy@9a000 { > + status = "ok"; > + }; > + > + usb3_hs_phy: hsphy@a6000 { > + status = "ok"; > + }; > + > + usb3: usb3@8af8800 { > + status = "ok"; > + }; > + > + usb2_hs_phy: hsphy@a8000 { > + status = "ok"; > + }; > + > + usb2: usb2@60f8800 { > + status = "ok"; > + }; > }; > }; > diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi > index b6e5203a210b..18e9c639514c 100644 > --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi > +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi > @@ -564,5 +564,79 @@ > "legacy"; > status = "disabled"; > }; > + > + usb3_ss_phy: ssphy@9a000 { > + compatible = "qcom,usb-ss-ipq4019-phy"; > + #phy-cells = <0>; > + reg = <0x9a000 0x800>; > + reg-names = "phy_base"; > + resets = <&gcc USB3_UNIPHY_PHY_ARES>; > + reset-names = "por_rst"; > + status = "disabled"; > + }; > + > + usb3_hs_phy: hsphy@a6000 { > + compatible = "qcom,usb-hs-ipq4019-phy"; > + #phy-cells = <0>; > + reg = <0xa6000 0x40>; > + reg-names = "phy_base"; > + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; > + reset-names = "por_rst", "srif_rst"; > + status = "disabled"; > + }; > + > + usb3@8af8800 { > + compatible = "qcom,dwc3"; > + reg = <0x8af8800 0x100>; > + #address-cells = <1>; > + #size-cells = <1>; > + clocks = <&gcc GCC_USB3_MASTER_CLK>, > + <&gcc GCC_USB3_SLEEP_CLK>, > + <&gcc GCC_USB3_MOCK_UTMI_CLK>; > + clock-names = "master", "sleep", "mock_utmi"; > + ranges; > + status = "disabled"; > + > + dwc3@8a00000 { > + compatible = "snps,dwc3"; > + reg = <0x8a00000 0xf8000>; > + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb3_hs_phy>, <&usb3_ss_phy>; > + phy-names = "usb2-phy", "usb3-phy"; > + dr_mode = "host"; > + }; > + }; > + > + usb2_hs_phy: hsphy@a8000 { > + compatible = "qcom,usb-hs-ipq4019-phy"; > + #phy-cells = <0>; > + reg = <0xa8000 0x40>; > + reg-names = "phy_base"; > + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; > + reset-names = "por_rst", "srif_rst"; > + status = "disabled"; > + }; > + > + usb2@60f8800 { > + compatible = "qcom,dwc3"; > + reg = <0x60f8800 0x100>; > + #address-cells = <1>; > + #size-cells = <1>; > + clocks = <&gcc GCC_USB2_MASTER_CLK>, > + <&gcc GCC_USB2_SLEEP_CLK>, > + <&gcc GCC_USB2_MOCK_UTMI_CLK>; > + clock-names = "master", "sleep", "mock_utmi"; > + ranges; > + status = "disabled"; > + > + dwc3@6000000 { > + compatible = "snps,dwc3"; > + reg = <0x6000000 0xf8000>; > + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&usb2_hs_phy>; > + phy-names = "usb2-phy"; > + dr_mode = "host"; > + }; > + }; > }; > }; > -- > 2.24.1 >
On Fri, Mar 27, 2020 at 11:12 PM Bjorn Andersson <bjorn.andersson@linaro.org> wrote: > > On Mon 27 Jan 13:23 PST 2020, Robert Marko wrote: > > > From: John Crispin <john@phrozen.org> > > > > Since we now have driver for the USB PHY, lets add the necessary nodes to DTSI. > > > > Signed-off-by: John Crispin <john@phrozen.org> > > Tested-by: Robert Marko <robert.marko@sartura.hr> > > Cc: Luka Perkov <luka.perkov@sartura.hr> > > Robert, I'm missing your Signed-off-by here (and I would like Kishon to > take the PHY before merging this). Solved in v4. Thanks > > Regards, > Bjorn > > > --- > > arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 20 +++++ > > arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++ > > 2 files changed, 94 insertions(+) > > > > diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi > > index 418f9a022336..2ee5f05d5a43 100644 > > --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi > > +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi > > @@ -109,5 +109,25 @@ > > wifi@a800000 { > > status = "ok"; > > }; > > + > > + usb3_ss_phy: ssphy@9a000 { > > + status = "ok"; > > + }; > > + > > + usb3_hs_phy: hsphy@a6000 { > > + status = "ok"; > > + }; > > + > > + usb3: usb3@8af8800 { > > + status = "ok"; > > + }; > > + > > + usb2_hs_phy: hsphy@a8000 { > > + status = "ok"; > > + }; > > + > > + usb2: usb2@60f8800 { > > + status = "ok"; > > + }; > > }; > > }; > > diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi > > index b6e5203a210b..18e9c639514c 100644 > > --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi > > +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi > > @@ -564,5 +564,79 @@ > > "legacy"; > > status = "disabled"; > > }; > > + > > + usb3_ss_phy: ssphy@9a000 { > > + compatible = "qcom,usb-ss-ipq4019-phy"; > > + #phy-cells = <0>; > > + reg = <0x9a000 0x800>; > > + reg-names = "phy_base"; > > + resets = <&gcc USB3_UNIPHY_PHY_ARES>; > > + reset-names = "por_rst"; > > + status = "disabled"; > > + }; > > + > > + usb3_hs_phy: hsphy@a6000 { > > + compatible = "qcom,usb-hs-ipq4019-phy"; > > + #phy-cells = <0>; > > + reg = <0xa6000 0x40>; > > + reg-names = "phy_base"; > > + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; > > + reset-names = "por_rst", "srif_rst"; > > + status = "disabled"; > > + }; > > + > > + usb3@8af8800 { > > + compatible = "qcom,dwc3"; > > + reg = <0x8af8800 0x100>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + clocks = <&gcc GCC_USB3_MASTER_CLK>, > > + <&gcc GCC_USB3_SLEEP_CLK>, > > + <&gcc GCC_USB3_MOCK_UTMI_CLK>; > > + clock-names = "master", "sleep", "mock_utmi"; > > + ranges; > > + status = "disabled"; > > + > > + dwc3@8a00000 { > > + compatible = "snps,dwc3"; > > + reg = <0x8a00000 0xf8000>; > > + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; > > + phys = <&usb3_hs_phy>, <&usb3_ss_phy>; > > + phy-names = "usb2-phy", "usb3-phy"; > > + dr_mode = "host"; > > + }; > > + }; > > + > > + usb2_hs_phy: hsphy@a8000 { > > + compatible = "qcom,usb-hs-ipq4019-phy"; > > + #phy-cells = <0>; > > + reg = <0xa8000 0x40>; > > + reg-names = "phy_base"; > > + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; > > + reset-names = "por_rst", "srif_rst"; > > + status = "disabled"; > > + }; > > + > > + usb2@60f8800 { > > + compatible = "qcom,dwc3"; > > + reg = <0x60f8800 0x100>; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + clocks = <&gcc GCC_USB2_MASTER_CLK>, > > + <&gcc GCC_USB2_SLEEP_CLK>, > > + <&gcc GCC_USB2_MOCK_UTMI_CLK>; > > + clock-names = "master", "sleep", "mock_utmi"; > > + ranges; > > + status = "disabled"; > > + > > + dwc3@6000000 { > > + compatible = "snps,dwc3"; > > + reg = <0x6000000 0xf8000>; > > + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; > > + phys = <&usb2_hs_phy>; > > + phy-names = "usb2-phy"; > > + dr_mode = "host"; > > + }; > > + }; > > }; > > }; > > -- > > 2.24.1 > >
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi index 418f9a022336..2ee5f05d5a43 100644 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi @@ -109,5 +109,25 @@ wifi@a800000 { status = "ok"; }; + + usb3_ss_phy: ssphy@9a000 { + status = "ok"; + }; + + usb3_hs_phy: hsphy@a6000 { + status = "ok"; + }; + + usb3: usb3@8af8800 { + status = "ok"; + }; + + usb2_hs_phy: hsphy@a8000 { + status = "ok"; + }; + + usb2: usb2@60f8800 { + status = "ok"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index b6e5203a210b..18e9c639514c 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -564,5 +564,79 @@ "legacy"; status = "disabled"; }; + + usb3_ss_phy: ssphy@9a000 { + compatible = "qcom,usb-ss-ipq4019-phy"; + #phy-cells = <0>; + reg = <0x9a000 0x800>; + reg-names = "phy_base"; + resets = <&gcc USB3_UNIPHY_PHY_ARES>; + reset-names = "por_rst"; + status = "disabled"; + }; + + usb3_hs_phy: hsphy@a6000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa6000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb3@8af8800 { + compatible = "qcom,dwc3"; + reg = <0x8af8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB3_MASTER_CLK>, + <&gcc GCC_USB3_SLEEP_CLK>, + <&gcc GCC_USB3_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@8a00000 { + compatible = "snps,dwc3"; + reg = <0x8a00000 0xf8000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_hs_phy>, <&usb3_ss_phy>; + phy-names = "usb2-phy", "usb3-phy"; + dr_mode = "host"; + }; + }; + + usb2_hs_phy: hsphy@a8000 { + compatible = "qcom,usb-hs-ipq4019-phy"; + #phy-cells = <0>; + reg = <0xa8000 0x40>; + reg-names = "phy_base"; + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + status = "disabled"; + }; + + usb2@60f8800 { + compatible = "qcom,dwc3"; + reg = <0x60f8800 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&gcc GCC_USB2_MASTER_CLK>, + <&gcc GCC_USB2_SLEEP_CLK>, + <&gcc GCC_USB2_MOCK_UTMI_CLK>; + clock-names = "master", "sleep", "mock_utmi"; + ranges; + status = "disabled"; + + dwc3@6000000 { + compatible = "snps,dwc3"; + reg = <0x6000000 0xf8000>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb2_hs_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + }; + }; }; };