Message ID | 1584880394-11184-2-git-send-email-yi.l.liu@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | vfio/pci: expose device's PASID capability to VMs | expand |
> From: Liu, Yi L <yi.l.liu@intel.com> > Sent: Sunday, March 22, 2020 8:33 PM > > From: Liu Yi L <yi.l.liu@intel.com> > > This patch exposes PCIe PASID capability to guest. Existing vfio_pci > driver hides it from guest by setting the capability length as 0 in > pci_ext_cap_length[]. > > This capability is required for vSVA enabling on pass-through PCIe > devices. should this be [PATCH 2/2], after you have the emulation in place? and it might be worthy of noting that PRI is already exposed, to avoid confusion from one like me that why two capabilities are emulated in this series while only one is being exposed.
> From: Tian, Kevin <kevin.tian@intel.com> > Sent: Tuesday, March 31, 2020 2:39 PM > To: Liu, Yi L <yi.l.liu@intel.com>; alex.williamson@redhat.com; > Subject: RE: [PATCH v1 1/2] vfio/pci: Expose PCIe PASID capability to guest > > > From: Liu, Yi L <yi.l.liu@intel.com> > > Sent: Sunday, March 22, 2020 8:33 PM > > > > From: Liu Yi L <yi.l.liu@intel.com> > > > > This patch exposes PCIe PASID capability to guest. Existing vfio_pci > > driver hides it from guest by setting the capability length as 0 in > > pci_ext_cap_length[]. > > > > This capability is required for vSVA enabling on pass-through PCIe > > devices. > > should this be [PATCH 2/2], after you have the emulation in place? oh, yes, I can re-sequence it. > and it might be worthy of noting that PRI is already exposed, to > avoid confusion from one like me that why two capabilities are > emulated in this series while only one is being exposed.
diff --git a/drivers/vfio/pci/vfio_pci_config.c b/drivers/vfio/pci/vfio_pci_config.c index 90c0b80..4b9af99 100644 --- a/drivers/vfio/pci/vfio_pci_config.c +++ b/drivers/vfio/pci/vfio_pci_config.c @@ -95,7 +95,7 @@ static const u16 pci_ext_cap_length[PCI_EXT_CAP_ID_MAX + 1] = { [PCI_EXT_CAP_ID_LTR] = PCI_EXT_CAP_LTR_SIZEOF, [PCI_EXT_CAP_ID_SECPCI] = 0, /* not yet */ [PCI_EXT_CAP_ID_PMUX] = 0, /* not yet */ - [PCI_EXT_CAP_ID_PASID] = 0, /* not yet */ + [PCI_EXT_CAP_ID_PASID] = PCI_EXT_CAP_PASID_SIZEOF, }; /*