| Message ID | 1585700362-11892-2-git-send-email-wanpengli@tencent.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2,1/2] KVM: X86: Filter out the broadcast dest for IPI fastpath | expand |
On 01/04/20 02:19, Wanpeng Li wrote: > - /* No delay here, so we always clear the pending bit */ > - val &= ~(1 << 12); > + /* Immediately clear Delivery Status in xAPIC mode */ > + if (!apic_x2apic_mode(apic)) > + val &= ~(1 << 12); This adds a conditional, and the old behavior was valid according to the SDM: "software should not assume the value returned by reading the ICR is the last written value". Paolo
Cc more people, On Wed, 1 Apr 2020 at 08:35, Paolo Bonzini <pbonzini@redhat.com> wrote: > > On 01/04/20 02:19, Wanpeng Li wrote: > > - /* No delay here, so we always clear the pending bit */ > > - val &= ~(1 << 12); > > + /* Immediately clear Delivery Status in xAPIC mode */ > > + if (!apic_x2apic_mode(apic)) > > + val &= ~(1 << 12); > > This adds a conditional, and the old behavior was valid according to the > SDM: "software should not assume the value returned by reading the ICR > is the last written value". Nadav, Sean, what do you think? Wanpeng
On Wed, 1 Apr 2020 at 08:35, Paolo Bonzini <pbonzini@redhat.com> wrote: > > On 01/04/20 02:19, Wanpeng Li wrote: > > - /* No delay here, so we always clear the pending bit */ > > - val &= ~(1 << 12); > > + /* Immediately clear Delivery Status in xAPIC mode */ > > + if (!apic_x2apic_mode(apic)) > > + val &= ~(1 << 12); > > This adds a conditional, and the old behavior was valid according to the > SDM: "software should not assume the value returned by reading the ICR > is the last written value". We can queue patch 1/2 separately to catch the merge window. :) Wanpeng
> On Mar 31, 2020, at 11:46 PM, Wanpeng Li <kernellwp@gmail.com> wrote: > > Cc more people, > On Wed, 1 Apr 2020 at 08:35, Paolo Bonzini <pbonzini@redhat.com> wrote: >> On 01/04/20 02:19, Wanpeng Li wrote: >>> - /* No delay here, so we always clear the pending bit */ >>> - val &= ~(1 << 12); >>> + /* Immediately clear Delivery Status in xAPIC mode */ >>> + if (!apic_x2apic_mode(apic)) >>> + val &= ~(1 << 12); >> >> This adds a conditional, and the old behavior was valid according to the >> SDM: "software should not assume the value returned by reading the ICR >> is the last written value". > > Nadav, Sean, what do you think? I do not know. But if you write a KVM unit-test, I can run it on bare-metal and give you feedback about how it behaves.
On Wed, Apr 01, 2020 at 05:40:03PM +0000, Nadav Amit wrote: > > On Mar 31, 2020, at 11:46 PM, Wanpeng Li <kernellwp@gmail.com> wrote: > > > > Cc more people, > > On Wed, 1 Apr 2020 at 08:35, Paolo Bonzini <pbonzini@redhat.com> wrote: > >> On 01/04/20 02:19, Wanpeng Li wrote: > >>> - /* No delay here, so we always clear the pending bit */ > >>> - val &= ~(1 << 12); > >>> + /* Immediately clear Delivery Status in xAPIC mode */ > >>> + if (!apic_x2apic_mode(apic)) > >>> + val &= ~(1 << 12); > >> > >> This adds a conditional, and the old behavior was valid according to the > >> SDM: "software should not assume the value returned by reading the ICR > >> is the last written value". > > > > Nadav, Sean, what do you think? > > I do not know. But if you write a KVM unit-test, I can run it on bare-metal > and give you feedback about how it behaves. I agree with Paolo, clearing the bit doesn't violate the SDM. The conditional is just as costly as the AND, if not more so, even for x2APIC. I would play it safe and clear the bit even in the x2APIC only path to avoid tripping up guest kernels that loop on the delivery status even when using x2APIC.
On Thu, 2 Apr 2020 at 07:01, Sean Christopherson <sean.j.christopherson@intel.com> wrote: > > On Wed, Apr 01, 2020 at 05:40:03PM +0000, Nadav Amit wrote: > > > On Mar 31, 2020, at 11:46 PM, Wanpeng Li <kernellwp@gmail.com> wrote: > > > > > > Cc more people, > > > On Wed, 1 Apr 2020 at 08:35, Paolo Bonzini <pbonzini@redhat.com> wrote: > > >> On 01/04/20 02:19, Wanpeng Li wrote: > > >>> - /* No delay here, so we always clear the pending bit */ > > >>> - val &= ~(1 << 12); > > >>> + /* Immediately clear Delivery Status in xAPIC mode */ > > >>> + if (!apic_x2apic_mode(apic)) > > >>> + val &= ~(1 << 12); > > >> > > >> This adds a conditional, and the old behavior was valid according to the > > >> SDM: "software should not assume the value returned by reading the ICR > > >> is the last written value". > > > > > > Nadav, Sean, what do you think? > > > > I do not know. But if you write a KVM unit-test, I can run it on bare-metal > > and give you feedback about how it behaves. > > I agree with Paolo, clearing the bit doesn't violate the SDM. The > conditional is just as costly as the AND, if not more so, even for x2APIC. > > I would play it safe and clear the bit even in the x2APIC only path to > avoid tripping up guest kernels that loop on the delivery status even when > using x2APIC. Fair enough. Wanpeng
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index d528bed..5efca58 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1941,8 +1941,9 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) break; } case APIC_ICR: - /* No delay here, so we always clear the pending bit */ - val &= ~(1 << 12); + /* Immediately clear Delivery Status in xAPIC mode */ + if (!apic_x2apic_mode(apic)) + val &= ~(1 << 12); kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2)); kvm_lapic_set_reg(apic, APIC_ICR, val); break; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 5a645df..ececc09 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1562,7 +1562,6 @@ static int handle_fastpath_set_x2apic_icr_irqoff(struct kvm_vcpu *vcpu, u64 data ((data & APIC_MODE_MASK) == APIC_DM_FIXED) && ((u32)(data >> 32) != X2APIC_BROADCAST)) { - data &= ~(1 << 12); kvm_apic_send_ipi(vcpu->arch.apic, (u32)data, (u32)(data >> 32)); kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR2, (u32)(data >> 32)); kvm_lapic_set_reg(vcpu->arch.apic, APIC_ICR, (u32)data);