| Message ID | 20200327071202.2159885-4-alastair@d-silva.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add support for OpenCAPI Persistent Memory devices | expand |
On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva <alastair@d-silva.org> wrote: > > This patch adds OPAL calls to powernv so that the OpenCAPI > driver can map & release LPC (Lowest Point of Coherency) memory. > > Signed-off-by: Alastair D'Silva <alastair@d-silva.org> > Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> > --- > arch/powerpc/include/asm/pnv-ocxl.h | 2 ++ > arch/powerpc/platforms/powernv/ocxl.c | 43 +++++++++++++++++++++++++++ > 2 files changed, 45 insertions(+) > > diff --git a/arch/powerpc/include/asm/pnv-ocxl.h b/arch/powerpc/include/asm/pnv-ocxl.h > index 7de82647e761..560a19bb71b7 100644 > --- a/arch/powerpc/include/asm/pnv-ocxl.h > +++ b/arch/powerpc/include/asm/pnv-ocxl.h > @@ -32,5 +32,7 @@ extern int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle) > > extern int pnv_ocxl_alloc_xive_irq(u32 *irq, u64 *trigger_addr); > extern void pnv_ocxl_free_xive_irq(u32 irq); > +u64 pnv_ocxl_platform_lpc_setup(struct pci_dev *pdev, u64 size); > +void pnv_ocxl_platform_lpc_release(struct pci_dev *pdev); > > #endif /* _ASM_PNV_OCXL_H */ > diff --git a/arch/powerpc/platforms/powernv/ocxl.c b/arch/powerpc/platforms/powernv/ocxl.c > index 8c65aacda9c8..f13119a7c026 100644 > --- a/arch/powerpc/platforms/powernv/ocxl.c > +++ b/arch/powerpc/platforms/powernv/ocxl.c > @@ -475,6 +475,49 @@ void pnv_ocxl_spa_release(void *platform_data) > } > EXPORT_SYMBOL_GPL(pnv_ocxl_spa_release); > > +u64 pnv_ocxl_platform_lpc_setup(struct pci_dev *pdev, u64 size) > +{ > + struct pci_controller *hose = pci_bus_to_host(pdev->bus); > + struct pnv_phb *phb = hose->private_data; Is calling the local variable 'hose' instead of 'host' on purpose? > + u32 bdfn = pci_dev_id(pdev); > + __be64 base_addr_be64; > + u64 base_addr; > + int rc; > + > + rc = opal_npu_mem_alloc(phb->opal_id, bdfn, size, &base_addr_be64); > + if (rc) { > + dev_warn(&pdev->dev, > + "OPAL could not allocate LPC memory, rc=%d\n", rc); > + return 0; > + } > + > + base_addr = be64_to_cpu(base_addr_be64); > + > +#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE With the proposed cleanup in patch2 the ifdef can be elided here. > + rc = check_hotplug_memory_addressable(base_addr >> PAGE_SHIFT, > + size >> PAGE_SHIFT); > + if (rc) > + return 0; Is this an error worth logging if someone is wondering why their device is not showing up? > +#endif > + > + return base_addr; > +} > +EXPORT_SYMBOL_GPL(pnv_ocxl_platform_lpc_setup); > + > +void pnv_ocxl_platform_lpc_release(struct pci_dev *pdev) > +{ > + struct pci_controller *hose = pci_bus_to_host(pdev->bus); > + struct pnv_phb *phb = hose->private_data; > + u32 bdfn = pci_dev_id(pdev); > + int rc; > + > + rc = opal_npu_mem_release(phb->opal_id, bdfn); > + if (rc) > + dev_warn(&pdev->dev, > + "OPAL reported rc=%d when releasing LPC memory\n", rc); > +} > +EXPORT_SYMBOL_GPL(pnv_ocxl_platform_lpc_release); > + > int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle) > { > struct spa_data *data = (struct spa_data *) platform_data; > -- > 2.24.1 >
> -----Original Message----- > From: Dan Williams <dan.j.williams@intel.com> > Sent: Wednesday, 1 April 2020 7:49 PM > To: Alastair D'Silva <alastair@d-silva.org> > Cc: Aneesh Kumar K . V <aneesh.kumar@linux.ibm.com>; Oliver O'Halloran > <oohall@gmail.com>; Benjamin Herrenschmidt > <benh@kernel.crashing.org>; Paul Mackerras <paulus@samba.org>; Michael > Ellerman <mpe@ellerman.id.au>; Frederic Barrat <fbarrat@linux.ibm.com>; > Andrew Donnellan <ajd@linux.ibm.com>; Arnd Bergmann > <arnd@arndb.de>; Greg Kroah-Hartman <gregkh@linuxfoundation.org>; > Vishal Verma <vishal.l.verma@intel.com>; Dave Jiang > <dave.jiang@intel.com>; Ira Weiny <ira.weiny@intel.com>; Andrew Morton > <akpm@linux-foundation.org>; Mauro Carvalho Chehab > <mchehab+samsung@kernel.org>; David S. Miller <davem@davemloft.net>; > Rob Herring <robh@kernel.org>; Anton Blanchard <anton@ozlabs.org>; > Krzysztof Kozlowski <krzk@kernel.org>; Mahesh Salgaonkar > <mahesh@linux.vnet.ibm.com>; Madhavan Srinivasan > <maddy@linux.vnet.ibm.com>; Cédric Le Goater <clg@kaod.org>; Anju T > Sudhakar <anju@linux.vnet.ibm.com>; Hari Bathini > <hbathini@linux.ibm.com>; Thomas Gleixner <tglx@linutronix.de>; Greg > Kurz <groug@kaod.org>; Nicholas Piggin <npiggin@gmail.com>; Masahiro > Yamada <yamada.masahiro@socionext.com>; Alexey Kardashevskiy > <aik@ozlabs.ru>; Linux Kernel Mailing List <linux-kernel@vger.kernel.org>; > linuxppc-dev <linuxppc-dev@lists.ozlabs.org>; linux-nvdimm <linux- > nvdimm@lists.01.org>; Linux MM <linux-mm@kvack.org> > Subject: Re: [PATCH v4 03/25] powerpc/powernv: Map & release OpenCAPI > LPC memory > > On Sun, Mar 29, 2020 at 10:23 PM Alastair D'Silva <alastair@d-silva.org> > wrote: > > > > This patch adds OPAL calls to powernv so that the OpenCAPI driver can > > map & release LPC (Lowest Point of Coherency) memory. > > > > Signed-off-by: Alastair D'Silva <alastair@d-silva.org> > > Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> > > --- > > arch/powerpc/include/asm/pnv-ocxl.h | 2 ++ > > arch/powerpc/platforms/powernv/ocxl.c | 43 > > +++++++++++++++++++++++++++ > > 2 files changed, 45 insertions(+) > > > > diff --git a/arch/powerpc/include/asm/pnv-ocxl.h > > b/arch/powerpc/include/asm/pnv-ocxl.h > > index 7de82647e761..560a19bb71b7 100644 > > --- a/arch/powerpc/include/asm/pnv-ocxl.h > > +++ b/arch/powerpc/include/asm/pnv-ocxl.h > > @@ -32,5 +32,7 @@ extern int > pnv_ocxl_spa_remove_pe_from_cache(void > > *platform_data, int pe_handle) > > > > extern int pnv_ocxl_alloc_xive_irq(u32 *irq, u64 *trigger_addr); > > extern void pnv_ocxl_free_xive_irq(u32 irq); > > +u64 pnv_ocxl_platform_lpc_setup(struct pci_dev *pdev, u64 size); void > > +pnv_ocxl_platform_lpc_release(struct pci_dev *pdev); > > > > #endif /* _ASM_PNV_OCXL_H */ > > diff --git a/arch/powerpc/platforms/powernv/ocxl.c > > b/arch/powerpc/platforms/powernv/ocxl.c > > index 8c65aacda9c8..f13119a7c026 100644 > > --- a/arch/powerpc/platforms/powernv/ocxl.c > > +++ b/arch/powerpc/platforms/powernv/ocxl.c > > @@ -475,6 +475,49 @@ void pnv_ocxl_spa_release(void *platform_data) > } > > EXPORT_SYMBOL_GPL(pnv_ocxl_spa_release); > > > > +u64 pnv_ocxl_platform_lpc_setup(struct pci_dev *pdev, u64 size) { > > + struct pci_controller *hose = pci_bus_to_host(pdev->bus); > > + struct pnv_phb *phb = hose->private_data; > > Is calling the local variable 'hose' instead of 'host' on purpose? > Yes, this follows the convention used in other functions in this file. > > + u32 bdfn = pci_dev_id(pdev); > > + __be64 base_addr_be64; > > + u64 base_addr; > > + int rc; > > + > > + rc = opal_npu_mem_alloc(phb->opal_id, bdfn, size, > &base_addr_be64); > > + if (rc) { > > + dev_warn(&pdev->dev, > > + "OPAL could not allocate LPC memory, rc=%d\n", rc); > > + return 0; > > + } > > + > > + base_addr = be64_to_cpu(base_addr_be64); > > + > > +#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE > > With the proposed cleanup in patch2 the ifdef can be elided here. Ok > > > + rc = check_hotplug_memory_addressable(base_addr >> PAGE_SHIFT, > > + size >> PAGE_SHIFT); > > + if (rc) > > + return 0; > > Is this an error worth logging if someone is wondering why their device is not > showing up? > Yes, I'll add a message. > > > +#endif > > + > > + return base_addr; > > +} > > +EXPORT_SYMBOL_GPL(pnv_ocxl_platform_lpc_setup); > > + > > +void pnv_ocxl_platform_lpc_release(struct pci_dev *pdev) { > > + struct pci_controller *hose = pci_bus_to_host(pdev->bus); > > + struct pnv_phb *phb = hose->private_data; > > + u32 bdfn = pci_dev_id(pdev); > > + int rc; > > + > > + rc = opal_npu_mem_release(phb->opal_id, bdfn); > > + if (rc) > > + dev_warn(&pdev->dev, > > + "OPAL reported rc=%d when releasing LPC > > +memory\n", rc); } > EXPORT_SYMBOL_GPL(pnv_ocxl_platform_lpc_release); > > + > > int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int > > pe_handle) { > > struct spa_data *data = (struct spa_data *) platform_data; > > -- > > 2.24.1 > > > > > -- > This email has been checked for viruses by AVG. > https://www.avg.com
Benjamin Herrenschmidt <benh@kernel.crashing.org> writes: > On Wed, 2020-04-01 at 01:48 -0700, Dan Williams wrote: >> > >> > +u64 pnv_ocxl_platform_lpc_setup(struct pci_dev *pdev, u64 size) >> > +{ >> > + struct pci_controller *hose = pci_bus_to_host(pdev->bus); >> > + struct pnv_phb *phb = hose->private_data; >> >> Is calling the local variable 'hose' instead of 'host' on purpose? > > Haha that's funny :-) > > It's an oooooooold usage that comes iirc from sparc ? or maybe alpha ? Yeah it was alpha, I found it in the history tree: https://github.com/mpe/linux-fullhistory/blob/1928de59ba4209dc5e9f2cef63560c09ba0df73b/arch/alpha/kernel/mcpcia.c And airlied found an old manual which confirms it: The TIOP module interfaces the AlphaServer 8000 system bus to four I/O channels, called "hoses." https://www.hpl.hp.com/hpjournal/dtj/vol7num1/vol7num1art4.pdf So at least now we know where it comes from. It's also used widely in mips, microblaze, sh and a little bit in drm. cheers
diff --git a/arch/powerpc/include/asm/pnv-ocxl.h b/arch/powerpc/include/asm/pnv-ocxl.h index 7de82647e761..560a19bb71b7 100644 --- a/arch/powerpc/include/asm/pnv-ocxl.h +++ b/arch/powerpc/include/asm/pnv-ocxl.h @@ -32,5 +32,7 @@ extern int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle) extern int pnv_ocxl_alloc_xive_irq(u32 *irq, u64 *trigger_addr); extern void pnv_ocxl_free_xive_irq(u32 irq); +u64 pnv_ocxl_platform_lpc_setup(struct pci_dev *pdev, u64 size); +void pnv_ocxl_platform_lpc_release(struct pci_dev *pdev); #endif /* _ASM_PNV_OCXL_H */ diff --git a/arch/powerpc/platforms/powernv/ocxl.c b/arch/powerpc/platforms/powernv/ocxl.c index 8c65aacda9c8..f13119a7c026 100644 --- a/arch/powerpc/platforms/powernv/ocxl.c +++ b/arch/powerpc/platforms/powernv/ocxl.c @@ -475,6 +475,49 @@ void pnv_ocxl_spa_release(void *platform_data) } EXPORT_SYMBOL_GPL(pnv_ocxl_spa_release); +u64 pnv_ocxl_platform_lpc_setup(struct pci_dev *pdev, u64 size) +{ + struct pci_controller *hose = pci_bus_to_host(pdev->bus); + struct pnv_phb *phb = hose->private_data; + u32 bdfn = pci_dev_id(pdev); + __be64 base_addr_be64; + u64 base_addr; + int rc; + + rc = opal_npu_mem_alloc(phb->opal_id, bdfn, size, &base_addr_be64); + if (rc) { + dev_warn(&pdev->dev, + "OPAL could not allocate LPC memory, rc=%d\n", rc); + return 0; + } + + base_addr = be64_to_cpu(base_addr_be64); + +#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE + rc = check_hotplug_memory_addressable(base_addr >> PAGE_SHIFT, + size >> PAGE_SHIFT); + if (rc) + return 0; +#endif + + return base_addr; +} +EXPORT_SYMBOL_GPL(pnv_ocxl_platform_lpc_setup); + +void pnv_ocxl_platform_lpc_release(struct pci_dev *pdev) +{ + struct pci_controller *hose = pci_bus_to_host(pdev->bus); + struct pnv_phb *phb = hose->private_data; + u32 bdfn = pci_dev_id(pdev); + int rc; + + rc = opal_npu_mem_release(phb->opal_id, bdfn); + if (rc) + dev_warn(&pdev->dev, + "OPAL reported rc=%d when releasing LPC memory\n", rc); +} +EXPORT_SYMBOL_GPL(pnv_ocxl_platform_lpc_release); + int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle) { struct spa_data *data = (struct spa_data *) platform_data;