@@ -197,6 +197,7 @@ enum loongson_bridge_type {
LS7A = 2
};
+struct pci_bus;
struct loongson_system_configuration {
u32 nr_cpus;
u32 nr_nodes;
@@ -222,6 +223,8 @@ struct loongson_system_configuration {
struct sensor_device sensors[MAX_SENSORS];
u64 workarounds;
void (*early_config)(void);
+ int (*pci_config_access)(unsigned char access_type, struct pci_bus *bus,
+ unsigned int devfn, int where, u32 *data);
};
extern struct efi_memory_map_loongson *loongson_memmap;
@@ -230,5 +233,11 @@ extern struct loongson_system_configuration loongson_sysconf;
extern u32 node_id_offset;
extern void rs780e_early_config(void);
extern void ls7a_early_config(void);
+extern int rs780e_pci_config_access(unsigned char access_type,
+ struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *data);
+extern int ls7a_pci_config_access(unsigned char access_type,
+ struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *data);
#endif
@@ -193,9 +193,11 @@ void __init prom_init_env(void)
pr_info("The bridge chip is LS7A\n");
loongson_sysconf.bridgetype = LS7A;
loongson_sysconf.early_config = ls7a_early_config;
+ loongson_sysconf.pci_config_access = ls7a_pci_config_access;
} else {
pr_info("The bridge chip is RS780E or SR5690\n");
loongson_sysconf.bridgetype = RS780E;
loongson_sysconf.early_config = rs780e_early_config;
+ loongson_sysconf.pci_config_access = rs780e_pci_config_access;
}
}
@@ -64,6 +64,18 @@ static void pci_fixup_radeon(struct pci_dev *pdev)
DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
+static void ls7a_pci_class_quirk(struct pci_dev *dev)
+{
+ dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 0x7a09,
+ ls7a_pci_class_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 0x7a19,
+ ls7a_pci_class_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, 0x7a29,
+ ls7a_pci_class_quirk);
+
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
@@ -13,7 +13,10 @@
#define HT1LO_PCICFG_BASE 0x1a000000
#define HT1LO_PCICFG_BASE_TP1 0x1b000000
-static int loongson3_pci_config_access(unsigned char access_type,
+#define HT1LO_PCICFG_BASE_EXT 0xefe00000000
+#define HT1LO_PCICFG_BASE_TP1_EXT 0xefe10000000
+
+int rs780e_pci_config_access(unsigned char access_type,
struct pci_bus *bus, unsigned int devfn,
int where, u32 *data)
{
@@ -62,11 +65,63 @@ static int loongson3_pci_config_access(unsigned char access_type,
return PCIBIOS_SUCCESSFUL;
}
+
+int ls7a_pci_config_access(unsigned char access_type,
+ struct pci_bus *bus, unsigned int devfn,
+ int where, u32 *data)
+{
+ u_int64_t addr;
+ void *addrp;
+ unsigned char busnum = bus->number;
+ int device = PCI_SLOT(devfn);
+ int function = PCI_FUNC(devfn);
+ int reg = where & ~3;
+
+ if (where >= PCI_CFG_SPACE_EXP_SIZE)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (busnum == 0 && device > 23)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+
+ if (where < PCI_CFG_SPACE_SIZE) { /* standard config */
+ addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
+ if (busnum == 0) {
+ addr = HT1LO_PCICFG_BASE | addr;
+ addrp = (void *)TO_UNCAC(addr);
+ } else {
+ addr = HT1LO_PCICFG_BASE_TP1 | addr;
+ addrp = (void *)TO_UNCAC(addr);
+ }
+ } else { /* extended config */
+ reg = (reg & 0xff) | ((reg & 0xf00) << 16);
+ addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
+ if (busnum == 0) {
+ addr = HT1LO_PCICFG_BASE_EXT | addr;
+ addrp = (void *)TO_UNCAC(addr);
+ } else {
+ addr = HT1LO_PCICFG_BASE_TP1_EXT | addr;
+ addrp = (void *)TO_UNCAC(addr);
+ }
+ }
+
+ if (access_type == PCI_ACCESS_WRITE)
+ *(unsigned int *)addrp = cpu_to_le32(*data);
+ else {
+ *data = le32_to_cpu(*(unsigned int *)addrp);
+ if (*data == 0xffffffff) {
+ *data = -1;
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+ }
+
+ return PCIBIOS_SUCCESSFUL;
+}
+
static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 *val)
{
u32 data = 0;
- int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
+ int ret = loongson_sysconf.pci_config_access(PCI_ACCESS_READ,
bus, devfn, where, &data);
if (ret != PCIBIOS_SUCCESSFUL)
@@ -91,7 +146,7 @@ static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
if (size == 4)
data = val;
else {
- ret = loongson3_pci_config_access(PCI_ACCESS_READ,
+ ret = loongson_sysconf.pci_config_access(PCI_ACCESS_READ,
bus, devfn, where, &data);
if (ret != PCIBIOS_SUCCESSFUL)
return ret;
@@ -104,7 +159,7 @@ static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
(val << ((where & 3) << 3));
}
- ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
+ ret = loongson_sysconf.pci_config_access(PCI_ACCESS_WRITE,
bus, devfn, where, &data);
return ret;
Add PCI support for LS7A to detect PCI device. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> --- v3: - Move ls7a1000_pci_class_quirk() to fixup-loongson3.c - Use PCI_VENDOR_ID_LOONGSON in pci_ids.h instead of 0x0014 PCI_VENDOR_ID_LOONGSON depends on the mainline tree's commit: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=9acb9fe18d86 v4: - Use LS7A instead of Loongson 7A1000 in the description - Use LS7A or ls7a instead of LS7A1000 or ls7a1000 in the code arch/mips/include/asm/mach-loongson64/boot_param.h | 9 ++++ arch/mips/loongson64/env.c | 2 + arch/mips/pci/fixup-loongson3.c | 12 +++++ arch/mips/pci/ops-loongson3.c | 63 ++++++++++++++++++++-- 4 files changed, 82 insertions(+), 4 deletions(-)