| Message ID | 20200331082725.81048-5-jitao.shi@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Config mipi tx current and impedance | expand |
Hi, Jitao: Jitao Shi <jitao.shi@mediatek.com> 於 2020年3月31日 週二 下午4:28寫道： > > Read calibration data from nvmem, and config mipitx impedance with > calibration data to make sure their impedance are 100ohm. > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++++++++++++++++++ > 1 file changed, 57 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > index e4cc967750cb..0f87cd3d1d7d 100644 > --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > @@ -5,6 +5,8 @@ > */ > > #include "mtk_mipi_tx.h" > +#include <linux/nvmem-consumer.h> > +#include <linux/slab.h> > > #define MIPITX_LANE_CON 0x000c > #define RG_DSI_CPHY_T1DRV_EN BIT(0) > @@ -28,6 +30,7 @@ > #define MIPITX_PLL_CON4 0x003c > #define RG_DSI_PLL_IBIAS (3 << 10) > > +#define MIPITX_D2P_RTCODE 0x0100 > #define MIPITX_D2_SW_CTL_EN 0x0144 > #define MIPITX_D0_SW_CTL_EN 0x0244 > #define MIPITX_CK_CKMODE_EN 0x0328 > @@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = { > .recalc_rate = mtk_mipi_tx_pll_recalc_rate, > }; > > +static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) > +{ > + u32 *buf; > + u32 rt_code[5]; > + int i, j; > + struct nvmem_cell *cell; > + struct device *dev = mipi_tx->dev; > + size_t len; > + > + cell = nvmem_cell_get(dev, "calibration-data"); > + if (IS_ERR(cell)) { > + dev_info(dev, "nvmem_cell_get fail\n"); > + return; > + } > + > + buf = (u32 *)nvmem_cell_read(cell, &len); > + > + nvmem_cell_put(cell); > + > + if (IS_ERR(buf)) { > + dev_info(dev, "can't get data\n"); > + return; > + } > + > + if (len < 3 * sizeof(u32)) { > + dev_info(dev, "invalid calibration data\n"); > + kfree(buf); > + return; > + } > + > + rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & 0x1f); > + rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & 0x1f); > + rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 & 0x1f); > + rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & 0x1f); > + rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & 0x1f); Why not just save rt_code in nvmem and you don't need to translate here? If you need to do so, please add description for this. Regards, Chun-Kuang. > + > + for (i = 0; i < 5; i++) { > + if ((rt_code[i] & 0x1f) == 0) > + rt_code[i] |= 0x10; > + > + if ((rt_code[i] >> 5 & 0x1f) == 0) > + rt_code[i] |= 0x10 << 5; > + > + for (j = 0; j < 10; j++) > + mtk_mipi_tx_update_bits(mipi_tx, > + MIPITX_D2P_RTCODE * (i + 1) + j * 4, > + 1, rt_code[i] >> j & 1); > + } > + > + kfree(buf); > +} > + > static void mtk_mipi_tx_power_on_signal(struct phy *phy) > { > struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); > @@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) > RG_DSI_HSTX_LDO_REF_SEL, > (mipi_tx->mipitx_drive - 3000) / 200 << 6); > > + mtk_mipi_tx_config_calibration_data(mipi_tx); > + > mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); > } > > -- > 2.21.0 > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel
On Sat, 2020-04-04 at 22:26 +0800, Chun-Kuang Hu wrote: > Hi, Jitao: > > Jitao Shi <jitao.shi@mediatek.com> 於 2020年3月31日 週二 下午4:28寫道： > > > > Read calibration data from nvmem, and config mipitx impedance with > > calibration data to make sure their impedance are 100ohm. > > > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++++++++++++++++++ > > 1 file changed, 57 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > > index e4cc967750cb..0f87cd3d1d7d 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > > +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > > @@ -5,6 +5,8 @@ > > */ > > > > #include "mtk_mipi_tx.h" > > +#include <linux/nvmem-consumer.h> > > +#include <linux/slab.h> > > > > #define MIPITX_LANE_CON 0x000c > > #define RG_DSI_CPHY_T1DRV_EN BIT(0) > > @@ -28,6 +30,7 @@ > > #define MIPITX_PLL_CON4 0x003c > > #define RG_DSI_PLL_IBIAS (3 << 10) > > > > +#define MIPITX_D2P_RTCODE 0x0100 > > #define MIPITX_D2_SW_CTL_EN 0x0144 > > #define MIPITX_D0_SW_CTL_EN 0x0244 > > #define MIPITX_CK_CKMODE_EN 0x0328 > > @@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = { > > .recalc_rate = mtk_mipi_tx_pll_recalc_rate, > > }; > > > > +static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) > > +{ > > + u32 *buf; > > + u32 rt_code[5]; > > + int i, j; > > + struct nvmem_cell *cell; > > + struct device *dev = mipi_tx->dev; > > + size_t len; > > + > > + cell = nvmem_cell_get(dev, "calibration-data"); > > + if (IS_ERR(cell)) { > > + dev_info(dev, "nvmem_cell_get fail\n"); > > + return; > > + } > > + > > + buf = (u32 *)nvmem_cell_read(cell, &len); > > + > > + nvmem_cell_put(cell); > > + > > + if (IS_ERR(buf)) { > > + dev_info(dev, "can't get data\n"); > > + return; > > + } > > + > > + if (len < 3 * sizeof(u32)) { > > + dev_info(dev, "invalid calibration data\n"); > > + kfree(buf); > > + return; > > + } > > + > > + rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & 0x1f); > > + rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & 0x1f); > > + rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 & 0x1f); > > + rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & 0x1f); > > + rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & 0x1f); > > Why not just save rt_code in nvmem and you don't need to translate here? > If you need to do so, please add description for this. > > Regards, > Chun-Kuang. > Hi Chun-Kuang, The calibration data is flashed in rom when the IC FT test And the data struct can't be stored again Best Regards JItao > > > + > > + for (i = 0; i < 5; i++) { > > + if ((rt_code[i] & 0x1f) == 0) > > + rt_code[i] |= 0x10; > > + > > + if ((rt_code[i] >> 5 & 0x1f) == 0) > > + rt_code[i] |= 0x10 << 5; > > + > > + for (j = 0; j < 10; j++) > > + mtk_mipi_tx_update_bits(mipi_tx, > > + MIPITX_D2P_RTCODE * (i + 1) + j * 4, > > + 1, rt_code[i] >> j & 1); > > + } > > + > > + kfree(buf); > > +} > > + > > static void mtk_mipi_tx_power_on_signal(struct phy *phy) > > { > > struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); > > @@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) > > RG_DSI_HSTX_LDO_REF_SEL, > > (mipi_tx->mipitx_drive - 3000) / 200 << 6); > > > > + mtk_mipi_tx_config_calibration_data(mipi_tx); > > + > > mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); > > } > > > > -- > > 2.21.0 > > _______________________________________________ > > dri-devel mailing list > > dri-devel@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
Hi, Jitao: Jitao Shi <jitao.shi@mediatek.com> 於 2020年4月5日 週日 下午9:39寫道： > > > On Sat, 2020-04-04 at 22:26 +0800, Chun-Kuang Hu wrote: > > Hi, Jitao: > > > > Jitao Shi <jitao.shi@mediatek.com> 於 2020年3月31日 週二 下午4:28寫道： > > > > > > Read calibration data from nvmem, and config mipitx impedance with > > > calibration data to make sure their impedance are 100ohm. > > > > > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > > > --- > > > drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++++++++++++++++++ > > > 1 file changed, 57 insertions(+) > > > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > > > index e4cc967750cb..0f87cd3d1d7d 100644 > > > --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > > > +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c > > > @@ -5,6 +5,8 @@ > > > */ > > > > > > #include "mtk_mipi_tx.h" > > > +#include <linux/nvmem-consumer.h> > > > +#include <linux/slab.h> > > > > > > #define MIPITX_LANE_CON 0x000c > > > #define RG_DSI_CPHY_T1DRV_EN BIT(0) > > > @@ -28,6 +30,7 @@ > > > #define MIPITX_PLL_CON4 0x003c > > > #define RG_DSI_PLL_IBIAS (3 << 10) > > > > > > +#define MIPITX_D2P_RTCODE 0x0100 > > > #define MIPITX_D2_SW_CTL_EN 0x0144 > > > #define MIPITX_D0_SW_CTL_EN 0x0244 > > > #define MIPITX_CK_CKMODE_EN 0x0328 > > > @@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = { > > > .recalc_rate = mtk_mipi_tx_pll_recalc_rate, > > > }; > > > > > > +static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) > > > +{ > > > + u32 *buf; > > > + u32 rt_code[5]; > > > + int i, j; > > > + struct nvmem_cell *cell; > > > + struct device *dev = mipi_tx->dev; > > > + size_t len; > > > + > > > + cell = nvmem_cell_get(dev, "calibration-data"); > > > + if (IS_ERR(cell)) { > > > + dev_info(dev, "nvmem_cell_get fail\n"); > > > + return; > > > + } > > > + > > > + buf = (u32 *)nvmem_cell_read(cell, &len); > > > + > > > + nvmem_cell_put(cell); > > > + > > > + if (IS_ERR(buf)) { > > > + dev_info(dev, "can't get data\n"); > > > + return; > > > + } > > > + > > > + if (len < 3 * sizeof(u32)) { > > > + dev_info(dev, "invalid calibration data\n"); > > > + kfree(buf); > > > + return; > > > + } > > > + > > > + rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & 0x1f); > > > + rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & 0x1f); > > > + rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 & 0x1f); > > > + rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & 0x1f); > > > + rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & 0x1f); > > > > Why not just save rt_code in nvmem and you don't need to translate here? > > If you need to do so, please add description for this. > > > > Regards, > > Chun-Kuang. > > > > Hi Chun-Kuang, > > The calibration data is flashed in rom when the IC FT test > And the data struct can't be stored again OK, it looks like this transtation is necessary. If it's fixed, I would like to get the rt_code when probe or somewhere initialization. Regards, Chun-Kuang. > > Best Regards > JItao > > > > > + > > > + for (i = 0; i < 5; i++) { > > > + if ((rt_code[i] & 0x1f) == 0) > > > + rt_code[i] |= 0x10; > > > + > > > + if ((rt_code[i] >> 5 & 0x1f) == 0) > > > + rt_code[i] |= 0x10 << 5; > > > + > > > + for (j = 0; j < 10; j++) > > > + mtk_mipi_tx_update_bits(mipi_tx, > > > + MIPITX_D2P_RTCODE * (i + 1) + j * 4, > > > + 1, rt_code[i] >> j & 1); > > > + } > > > + > > > + kfree(buf); > > > +} > > > + > > > static void mtk_mipi_tx_power_on_signal(struct phy *phy) > > > { > > > struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); > > > @@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) > > > RG_DSI_HSTX_LDO_REF_SEL, > > > (mipi_tx->mipitx_drive - 3000) / 200 << 6); > > > > > > + mtk_mipi_tx_config_calibration_data(mipi_tx); > > > + > > > mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); > > > } > > > > > > -- > > > 2.21.0 > > > _______________________________________________ > > > dri-devel mailing list > > > dri-devel@lists.freedesktop.org > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel > >
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c index e4cc967750cb..0f87cd3d1d7d 100644 --- a/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c +++ b/drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c @@ -5,6 +5,8 @@ */ #include "mtk_mipi_tx.h" +#include <linux/nvmem-consumer.h> +#include <linux/slab.h> #define MIPITX_LANE_CON 0x000c #define RG_DSI_CPHY_T1DRV_EN BIT(0) @@ -28,6 +30,7 @@ #define MIPITX_PLL_CON4 0x003c #define RG_DSI_PLL_IBIAS (3 << 10) +#define MIPITX_D2P_RTCODE 0x0100 #define MIPITX_D2_SW_CTL_EN 0x0144 #define MIPITX_D0_SW_CTL_EN 0x0244 #define MIPITX_CK_CKMODE_EN 0x0328 @@ -108,6 +111,58 @@ static const struct clk_ops mtk_mipi_tx_pll_ops = { .recalc_rate = mtk_mipi_tx_pll_recalc_rate, }; +static void mtk_mipi_tx_config_calibration_data(struct mtk_mipi_tx *mipi_tx) +{ + u32 *buf; + u32 rt_code[5]; + int i, j; + struct nvmem_cell *cell; + struct device *dev = mipi_tx->dev; + size_t len; + + cell = nvmem_cell_get(dev, "calibration-data"); + if (IS_ERR(cell)) { + dev_info(dev, "nvmem_cell_get fail\n"); + return; + } + + buf = (u32 *)nvmem_cell_read(cell, &len); + + nvmem_cell_put(cell); + + if (IS_ERR(buf)) { + dev_info(dev, "can't get data\n"); + return; + } + + if (len < 3 * sizeof(u32)) { + dev_info(dev, "invalid calibration data\n"); + kfree(buf); + return; + } + + rt_code[0] = ((buf[0] >> 6 & 0x1f) << 5) | (buf[0] >> 11 & 0x1f); + rt_code[1] = ((buf[1] >> 27 & 0x1f) << 5) | (buf[0] >> 1 & 0x1f); + rt_code[2] = ((buf[1] >> 17 & 0x1f) << 5) | (buf[1] >> 22 & 0x1f); + rt_code[3] = ((buf[1] >> 7 & 0x1f) << 5) | (buf[1] >> 12 & 0x1f); + rt_code[4] = ((buf[2] >> 27 & 0x1f) << 5) | (buf[1] >> 2 & 0x1f); + + for (i = 0; i < 5; i++) { + if ((rt_code[i] & 0x1f) == 0) + rt_code[i] |= 0x10; + + if ((rt_code[i] >> 5 & 0x1f) == 0) + rt_code[i] |= 0x10 << 5; + + for (j = 0; j < 10; j++) + mtk_mipi_tx_update_bits(mipi_tx, + MIPITX_D2P_RTCODE * (i + 1) + j * 4, + 1, rt_code[i] >> j & 1); + } + + kfree(buf); +} + static void mtk_mipi_tx_power_on_signal(struct phy *phy) { struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); @@ -130,6 +185,8 @@ static void mtk_mipi_tx_power_on_signal(struct phy *phy) RG_DSI_HSTX_LDO_REF_SEL, (mipi_tx->mipitx_drive - 3000) / 200 << 6); + mtk_mipi_tx_config_calibration_data(mipi_tx); + mtk_mipi_tx_set_bits(mipi_tx, MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); }
Read calibration data from nvmem, and config mipitx impedance with calibration data to make sure their impedance are 100ohm. Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_mt8183_mipi_tx.c | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+)