| Message ID | 20200401163542.83278-2-robert.marko@sartura.hr (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v6,1/3] phy: add driver for Qualcomm IPQ40xx USB PHY | expand |
On Wed, Apr 01, 2020 at 06:35:43PM +0200, Robert Marko wrote: > This patch adds the binding documentation for the HS/SS USB PHY found > inside Qualcom Dakota SoCs. > > Signed-off-by: John Crispin <john@phrozen.org> > Signed-off-by: Robert Marko <robert.marko@sartura.hr> > Cc: Luka Perkov <luka.perkov@sartura.hr> > --- > Changes from v5 to v6: > * Add missing include for reset defines in example > * Fix warning for missing # in #phy-cells > > Changes from v4 to v5: > * Replace tabs with whitespaces > * Add maintainer property > > .../bindings/phy/qcom-usb-ipq4019-phy.yaml | 50 +++++++++++++++++++ > 1 file changed, 50 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml b/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml new file mode 100644 index 000000000000..1118fe69b611 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-usb-ipq4019-phy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/phy/qcom-usb-ipq4019-phy.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcom IPQ40xx Dakota HS/SS USB PHY + +maintainers: + - Robert Marko <robert.marko@sartura.hr> + +properties: + compatible: + enum: + - qcom,usb-ss-ipq4019-phy + - qcom,usb-hs-ipq4019-phy + + reg: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: por_rst + - const: srif_rst + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - resets + - reset-names + - "#phy-cells" + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq4019.h> + + hsphy@a8000 { + #phy-cells = <0>; + compatible = "qcom,usb-hs-ipq4019-phy"; + reg = <0xa8000 0x40>; + resets = <&gcc USB2_HSPHY_POR_ARES>, + <&gcc USB2_HSPHY_S_ARES>; + reset-names = "por_rst", "srif_rst"; + };