| Message ID | 1584279836-29825-1-git-send-email-aisheng.dong@nxp.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | clk: imx8: add new clock binding for better pm support | expand |
Hi Stephen, > From: Dong Aisheng <aisheng.dong@nxp.com> > Sent: Sunday, March 15, 2020 9:44 PM > > This patch series is a preparation for the MX8 Architecture improvement. > As for IMX SCU based platforms like MX8QM and MX8QXP, they are comprised > of a couple of SS(Subsystems) while most of them within the same SS can be > shared. e.g. Clocks, Devices and etc. > > However, current clock binding is using SW IDs for device tree to use which can > cause troubles in writing the common <soc>-ss-xx.dtsi file for different SoCs. > > This patch series aims to introduce a new binding which is more close to > hardware and platform independent and can makes us write a more general > drivers for different SCU based SoCs. > > Another important thing is that on MX8, each Clock resource is associated with > a power domain. So we have to attach that clock device to the power domain in > order to make it work properly. Further more, the clock state will be lost when > its power domain is completely off during suspend/resume, so we also introduce > the clock state save&restore mechanism. > > It's based on latest shanw/for-next branch. > > The top commit is: > 4559a11e48d5 Merge branch 'imx/defconfig' into for-next > I carefully went through all your review comments on V4 [1] and i'm sure all of them have been addressed. And for the V5-Resend version [2] , we didn't receive your comment. It seems Shawn is also waiting for your feedback for the next step. Could you help check V6? For V6, only a minor update that added scu clk unregister if met error. As the original code does not support it, so i added an extra patch to handle it. [1] https://lore.kernel.org/linux-clk/AM0PR04MB421181E4376070636898906F80A10@AM0PR04MB4211.eurprd04.prod.outlook.com/t/ [2] https://patchwork.kernel.org/cover/11248249/ Regards Aisheng > ChangeLog: > v5->v6: > * add scu clk unregister if add provider failed > v4->v5: > * Address all comments from Stephen > v3->v4: > * use clk-indices for LPCG to fetch each clks offset from dt > v2->v3: > * change scu clk into two cells binding > * add clk pm patches to ease the understand of the changes > v1->v2: > * SCU clock changed to one cell clock binding inspired by arm,scpi.txt > Documentation/devicetree/bindings/arm/arm,scpi.txt > * Add required power domain property > * Dropped PATCH 3&4 first, will send the updated version accordingly > after the binding is finally determined, > > > Dong Aisheng (12): > dt-bindings: firmware: imx-scu: new binding to parse clocks from > device tree > dt-bindings: clock: imx-lpcg: add support to parse clocks from device > tree > clk: imx: scu: add two cells binding support > clk: imx: scu: bypass cpu power domains > clk: imx: scu: allow scu clk to take device pointer > clk: imx: scu: add runtime pm support > clk: imx: scu: add suspend/resume support > clk: imx: imx8qxp-lpcg: add parsing clocks from device tree > clk: imx: lpcg: allow lpcg clk to take device pointer > clk: imx: clk-imx8qxp-lpcg: add runtime pm support > clk: imx: lpcg: add suspend/resume support > clk: imx: scu: unregister clocks if add provider failed > > .../bindings/arm/freescale/fsl,scu.txt | 12 +- > .../bindings/clock/imx8qxp-lpcg.txt | 36 ++- > drivers/clk/imx/clk-imx8qxp-lpcg.c | 139 +++++++++++ > drivers/clk/imx/clk-imx8qxp.c | 136 ++++++----- > drivers/clk/imx/clk-lpcg-scu.c | 53 +++- > drivers/clk/imx/clk-scu.c | 231 +++++++++++++++++- > drivers/clk/imx/clk-scu.h | 56 ++++- > include/dt-bindings/clock/imx8-lpcg.h | 14 ++ > include/dt-bindings/firmware/imx/rsrc.h | 23 ++ > 9 files changed, 610 insertions(+), 90 deletions(-) create mode 100644 > include/dt-bindings/clock/imx8-lpcg.h > > -- > 2.23.0
Ping > From: Aisheng Dong <aisheng.dong@nxp.com> > Sent: Sunday, March 15, 2020 10:11 PM > > Hi Stephen, > > > From: Dong Aisheng <aisheng.dong@nxp.com> > > Sent: Sunday, March 15, 2020 9:44 PM > > > > This patch series is a preparation for the MX8 Architecture improvement. > > As for IMX SCU based platforms like MX8QM and MX8QXP, they are > > comprised of a couple of SS(Subsystems) while most of them within the > > same SS can be shared. e.g. Clocks, Devices and etc. > > > > However, current clock binding is using SW IDs for device tree to use > > which can cause troubles in writing the common <soc>-ss-xx.dtsi file for > different SoCs. > > > > This patch series aims to introduce a new binding which is more close > > to hardware and platform independent and can makes us write a more > > general drivers for different SCU based SoCs. > > > > Another important thing is that on MX8, each Clock resource is > > associated with a power domain. So we have to attach that clock device > > to the power domain in order to make it work properly. Further more, > > the clock state will be lost when its power domain is completely off > > during suspend/resume, so we also introduce the clock state save&restore > mechanism. > > > > It's based on latest shanw/for-next branch. > > > > The top commit is: > > 4559a11e48d5 Merge branch 'imx/defconfig' into for-next > > > > I carefully went through all your review comments on V4 [1] and i'm sure all of > them have been addressed. > And for the V5-Resend version [2] , we didn't receive your comment. > It seems Shawn is also waiting for your feedback for the next step. > Could you help check V6? > > For V6, only a minor update that added scu clk unregister if met error. As the > original code does not support it, so i added an extra patch to handle it. > > [1] > https://lore.kernel.org/linux-clk/AM0PR04MB421181E4376070636898906F80 > A10@AM0PR04MB4211.eurprd04.prod.outlook.com/t/ > [2] https://patchwork.kernel.org/cover/11248249/ > > Regards > Aisheng > > > ChangeLog: > > v5->v6: > > * add scu clk unregister if add provider failed > > v4->v5: > > * Address all comments from Stephen > > v3->v4: > > * use clk-indices for LPCG to fetch each clks offset from dt > > v2->v3: > > * change scu clk into two cells binding > > * add clk pm patches to ease the understand of the changes > > v1->v2: > > * SCU clock changed to one cell clock binding inspired by arm,scpi.txt > > Documentation/devicetree/bindings/arm/arm,scpi.txt > > * Add required power domain property > > * Dropped PATCH 3&4 first, will send the updated version accordingly > > after the binding is finally determined, > > > > > > Dong Aisheng (12): > > dt-bindings: firmware: imx-scu: new binding to parse clocks from > > device tree > > dt-bindings: clock: imx-lpcg: add support to parse clocks from device > > tree > > clk: imx: scu: add two cells binding support > > clk: imx: scu: bypass cpu power domains > > clk: imx: scu: allow scu clk to take device pointer > > clk: imx: scu: add runtime pm support > > clk: imx: scu: add suspend/resume support > > clk: imx: imx8qxp-lpcg: add parsing clocks from device tree > > clk: imx: lpcg: allow lpcg clk to take device pointer > > clk: imx: clk-imx8qxp-lpcg: add runtime pm support > > clk: imx: lpcg: add suspend/resume support > > clk: imx: scu: unregister clocks if add provider failed > > > > .../bindings/arm/freescale/fsl,scu.txt | 12 +- > > .../bindings/clock/imx8qxp-lpcg.txt | 36 ++- > > drivers/clk/imx/clk-imx8qxp-lpcg.c | 139 +++++++++++ > > drivers/clk/imx/clk-imx8qxp.c | 136 ++++++----- > > drivers/clk/imx/clk-lpcg-scu.c | 53 +++- > > drivers/clk/imx/clk-scu.c | 231 > +++++++++++++++++- > > drivers/clk/imx/clk-scu.h | 56 ++++- > > include/dt-bindings/clock/imx8-lpcg.h | 14 ++ > > include/dt-bindings/firmware/imx/rsrc.h | 23 ++ > > 9 files changed, 610 insertions(+), 90 deletions(-) create mode > > 100644 include/dt-bindings/clock/imx8-lpcg.h > > > > -- > > 2.23.0
Ping... This patchset is pending for quite a long time without comments. It also blocked a lot continued upstreaming work. Any suggestions how to proceed? Regards Aisheng > From: Aisheng Dong <aisheng.dong@nxp.com> > Sent: Thursday, March 26, 2020 11:15 AM > > Ping > > > From: Aisheng Dong <aisheng.dong@nxp.com> > > Sent: Sunday, March 15, 2020 10:11 PM > > > > Hi Stephen, > > > > > From: Dong Aisheng <aisheng.dong@nxp.com> > > > Sent: Sunday, March 15, 2020 9:44 PM > > > > > > This patch series is a preparation for the MX8 Architecture improvement. > > > As for IMX SCU based platforms like MX8QM and MX8QXP, they are > > > comprised of a couple of SS(Subsystems) while most of them within > > > the same SS can be shared. e.g. Clocks, Devices and etc. > > > > > > However, current clock binding is using SW IDs for device tree to > > > use which can cause troubles in writing the common <soc>-ss-xx.dtsi > > > file for > > different SoCs. > > > > > > This patch series aims to introduce a new binding which is more > > > close to hardware and platform independent and can makes us write a > > > more general drivers for different SCU based SoCs. > > > > > > Another important thing is that on MX8, each Clock resource is > > > associated with a power domain. So we have to attach that clock > > > device to the power domain in order to make it work properly. > > > Further more, the clock state will be lost when its power domain is > > > completely off during suspend/resume, so we also introduce the clock > > > state save&restore > > mechanism. > > > > > > It's based on latest shanw/for-next branch. > > > > > > The top commit is: > > > 4559a11e48d5 Merge branch 'imx/defconfig' into for-next > > > > > > > I carefully went through all your review comments on V4 [1] and i'm > > sure all of them have been addressed. > > And for the V5-Resend version [2] , we didn't receive your comment. > > It seems Shawn is also waiting for your feedback for the next step. > > Could you help check V6? > > > > For V6, only a minor update that added scu clk unregister if met > > error. As the original code does not support it, so i added an extra patch to > handle it. > > > > [1] > > > https://lore.kernel.org/linux-clk/AM0PR04MB421181E4376070636898906F80 > > A10@AM0PR04MB4211.eurprd04.prod.outlook.com/t/ > > [2] https://patchwork.kernel.org/cover/11248249/ > > > > Regards > > Aisheng > > > > > ChangeLog: > > > v5->v6: > > > * add scu clk unregister if add provider failed > > > v4->v5: > > > * Address all comments from Stephen > > > v3->v4: > > > * use clk-indices for LPCG to fetch each clks offset from dt > > > v2->v3: > > > * change scu clk into two cells binding > > > * add clk pm patches to ease the understand of the changes > > > v1->v2: > > > * SCU clock changed to one cell clock binding inspired by arm,scpi.txt > > > Documentation/devicetree/bindings/arm/arm,scpi.txt > > > * Add required power domain property > > > * Dropped PATCH 3&4 first, will send the updated version accordingly > > > after the binding is finally determined, > > > > > > > > > Dong Aisheng (12): > > > dt-bindings: firmware: imx-scu: new binding to parse clocks from > > > device tree > > > dt-bindings: clock: imx-lpcg: add support to parse clocks from device > > > tree > > > clk: imx: scu: add two cells binding support > > > clk: imx: scu: bypass cpu power domains > > > clk: imx: scu: allow scu clk to take device pointer > > > clk: imx: scu: add runtime pm support > > > clk: imx: scu: add suspend/resume support > > > clk: imx: imx8qxp-lpcg: add parsing clocks from device tree > > > clk: imx: lpcg: allow lpcg clk to take device pointer > > > clk: imx: clk-imx8qxp-lpcg: add runtime pm support > > > clk: imx: lpcg: add suspend/resume support > > > clk: imx: scu: unregister clocks if add provider failed > > > > > > .../bindings/arm/freescale/fsl,scu.txt | 12 +- > > > .../bindings/clock/imx8qxp-lpcg.txt | 36 ++- > > > drivers/clk/imx/clk-imx8qxp-lpcg.c | 139 +++++++++++ > > > drivers/clk/imx/clk-imx8qxp.c | 136 ++++++----- > > > drivers/clk/imx/clk-lpcg-scu.c | 53 +++- > > > drivers/clk/imx/clk-scu.c | 231 > > +++++++++++++++++- > > > drivers/clk/imx/clk-scu.h | 56 ++++- > > > include/dt-bindings/clock/imx8-lpcg.h | 14 ++ > > > include/dt-bindings/firmware/imx/rsrc.h | 23 ++ > > > 9 files changed, 610 insertions(+), 90 deletions(-) create mode > > > 100644 include/dt-bindings/clock/imx8-lpcg.h > > > > > > -- > > > 2.23.0
Gently Ping.. This patchset is without comments for a few months. Could you help this? > From: Aisheng Dong <aisheng.dong@nxp.com> > Sent: Tuesday, April 7, 2020 10:23 AM > > Ping... This patchset is pending for quite a long time without comments. It also > blocked a lot continued upstreaming work. > Any suggestions how to proceed? > > Regards > Aisheng > > > From: Aisheng Dong <aisheng.dong@nxp.com> > > Sent: Thursday, March 26, 2020 11:15 AM > > > > Ping > > > > > From: Aisheng Dong <aisheng.dong@nxp.com> > > > Sent: Sunday, March 15, 2020 10:11 PM > > > > > > Hi Stephen, > > > > > > > From: Dong Aisheng <aisheng.dong@nxp.com> > > > > Sent: Sunday, March 15, 2020 9:44 PM > > > > > > > > This patch series is a preparation for the MX8 Architecture improvement. > > > > As for IMX SCU based platforms like MX8QM and MX8QXP, they are > > > > comprised of a couple of SS(Subsystems) while most of them within > > > > the same SS can be shared. e.g. Clocks, Devices and etc. > > > > > > > > However, current clock binding is using SW IDs for device tree to > > > > use which can cause troubles in writing the common > > > > <soc>-ss-xx.dtsi file for > > > different SoCs. > > > > > > > > This patch series aims to introduce a new binding which is more > > > > close to hardware and platform independent and can makes us write > > > > a more general drivers for different SCU based SoCs. > > > > > > > > Another important thing is that on MX8, each Clock resource is > > > > associated with a power domain. So we have to attach that clock > > > > device to the power domain in order to make it work properly. > > > > Further more, the clock state will be lost when its power domain > > > > is completely off during suspend/resume, so we also introduce the > > > > clock state save&restore > > > mechanism. > > > > > > > > It's based on latest shanw/for-next branch. > > > > > > > > The top commit is: > > > > 4559a11e48d5 Merge branch 'imx/defconfig' into for-next > > > > > > > > > > I carefully went through all your review comments on V4 [1] and i'm > > > sure all of them have been addressed. > > > And for the V5-Resend version [2] , we didn't receive your comment. > > > It seems Shawn is also waiting for your feedback for the next step. > > > Could you help check V6? > > > > > > For V6, only a minor update that added scu clk unregister if met > > > error. As the original code does not support it, so i added an extra > > > patch to > > handle it. > > > > > > [1] > > > > > > https://lore.kernel.org/linux-clk/AM0PR04MB421181E4376070636898906F80 > > > A10@AM0PR04MB4211.eurprd04.prod.outlook.com/t/ > > > [2] https://patchwork.kernel.org/cover/11248249/ > > > > > > Regards > > > Aisheng > > > > > > > ChangeLog: > > > > v5->v6: > > > > * add scu clk unregister if add provider failed > > > > v4->v5: > > > > * Address all comments from Stephen > > > > v3->v4: > > > > * use clk-indices for LPCG to fetch each clks offset from dt > > > > v2->v3: > > > > * change scu clk into two cells binding > > > > * add clk pm patches to ease the understand of the changes > > > > v1->v2: > > > > * SCU clock changed to one cell clock binding inspired by arm,scpi.txt > > > > Documentation/devicetree/bindings/arm/arm,scpi.txt > > > > * Add required power domain property > > > > * Dropped PATCH 3&4 first, will send the updated version accordingly > > > > after the binding is finally determined, > > > > > > > > > > > > Dong Aisheng (12): > > > > dt-bindings: firmware: imx-scu: new binding to parse clocks from > > > > device tree > > > > dt-bindings: clock: imx-lpcg: add support to parse clocks from device > > > > tree > > > > clk: imx: scu: add two cells binding support > > > > clk: imx: scu: bypass cpu power domains > > > > clk: imx: scu: allow scu clk to take device pointer > > > > clk: imx: scu: add runtime pm support > > > > clk: imx: scu: add suspend/resume support > > > > clk: imx: imx8qxp-lpcg: add parsing clocks from device tree > > > > clk: imx: lpcg: allow lpcg clk to take device pointer > > > > clk: imx: clk-imx8qxp-lpcg: add runtime pm support > > > > clk: imx: lpcg: add suspend/resume support > > > > clk: imx: scu: unregister clocks if add provider failed > > > > > > > > .../bindings/arm/freescale/fsl,scu.txt | 12 +- > > > > .../bindings/clock/imx8qxp-lpcg.txt | 36 ++- > > > > drivers/clk/imx/clk-imx8qxp-lpcg.c | 139 +++++++++++ > > > > drivers/clk/imx/clk-imx8qxp.c | 136 ++++++----- > > > > drivers/clk/imx/clk-lpcg-scu.c | 53 +++- > > > > drivers/clk/imx/clk-scu.c | 231 > > > +++++++++++++++++- > > > > drivers/clk/imx/clk-scu.h | 56 ++++- > > > > include/dt-bindings/clock/imx8-lpcg.h | 14 ++ > > > > include/dt-bindings/firmware/imx/rsrc.h | 23 ++ > > > > 9 files changed, 610 insertions(+), 90 deletions(-) create mode > > > > 100644 include/dt-bindings/clock/imx8-lpcg.h > > > > > > > > -- > > > > 2.23.0
This patch series is a preparation for the MX8 Architecture improvement. As for IMX SCU based platforms like MX8QM and MX8QXP, they are comprised of a couple of SS(Subsystems) while most of them within the same SS can be shared. e.g. Clocks, Devices and etc. However, current clock binding is using SW IDs for device tree to use which can cause troubles in writing the common <soc>-ss-xx.dtsi file for different SoCs. This patch series aims to introduce a new binding which is more close to hardware and platform independent and can makes us write a more general drivers for different SCU based SoCs. Another important thing is that on MX8, each Clock resource is associated with a power domain. So we have to attach that clock device to the power domain in order to make it work properly. Further more, the clock state will be lost when its power domain is completely off during suspend/resume, so we also introduce the clock state save&restore mechanism. It's based on latest shanw/for-next branch. The top commit is: 4559a11e48d5 Merge branch 'imx/defconfig' into for-next ChangeLog: v5->v6: * add scu clk unregister if add provider failed v4->v5: * Address all comments from Stephen v3->v4: * use clk-indices for LPCG to fetch each clks offset from dt v2->v3: * change scu clk into two cells binding * add clk pm patches to ease the understand of the changes v1->v2: * SCU clock changed to one cell clock binding inspired by arm,scpi.txt Documentation/devicetree/bindings/arm/arm,scpi.txt * Add required power domain property * Dropped PATCH 3&4 first, will send the updated version accordingly after the binding is finally determined, Dong Aisheng (12): dt-bindings: firmware: imx-scu: new binding to parse clocks from device tree dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree clk: imx: scu: add two cells binding support clk: imx: scu: bypass cpu power domains clk: imx: scu: allow scu clk to take device pointer clk: imx: scu: add runtime pm support clk: imx: scu: add suspend/resume support clk: imx: imx8qxp-lpcg: add parsing clocks from device tree clk: imx: lpcg: allow lpcg clk to take device pointer clk: imx: clk-imx8qxp-lpcg: add runtime pm support clk: imx: lpcg: add suspend/resume support clk: imx: scu: unregister clocks if add provider failed .../bindings/arm/freescale/fsl,scu.txt | 12 +- .../bindings/clock/imx8qxp-lpcg.txt | 36 ++- drivers/clk/imx/clk-imx8qxp-lpcg.c | 139 +++++++++++ drivers/clk/imx/clk-imx8qxp.c | 136 ++++++----- drivers/clk/imx/clk-lpcg-scu.c | 53 +++- drivers/clk/imx/clk-scu.c | 231 +++++++++++++++++- drivers/clk/imx/clk-scu.h | 56 ++++- include/dt-bindings/clock/imx8-lpcg.h | 14 ++ include/dt-bindings/firmware/imx/rsrc.h | 23 ++ 9 files changed, 610 insertions(+), 90 deletions(-) create mode 100644 include/dt-bindings/clock/imx8-lpcg.h