| Message ID | 1580215149-21492-1-git-send-email-anshuman.khandual@arm.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Introduce ID_PFR2 and other CPU feature changes | expand |
On 01/28/2020 06:09 PM, Anshuman Khandual wrote: > This series is primarily motivated from an adhoc list from Mark Rutland > during our ID_ISAR6 discussion [1]. Besides, it also includes a patch > which does macro replacement for various open bits shift encodings in > various CPU ID registers. This series is based on linux-next 20200124. > > [1] https://patchwork.kernel.org/patch/11287805/ > > Is there anything else apart from these changes which can be accommodated > in this series, please do let me know. Thank you. Just a gentle ping. Any updates, does this series looks okay ? Is there anything else related to CPU ID register feature bits, which can be added up here. FWIW, the series still applies on v5.6-rc1. > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: James Morse <james.morse@arm.com> > Cc: Suzuki K Poulose <suzuki.poulose@arm.com> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: kvmarm@lists.cs.columbia.edu > Cc: linux-kernel@vger.kernel.org > > Anshuman Khandual (6): > arm64/cpufeature: Introduce ID_PFR2 CPU register > arm64/cpufeature: Add DIT and CSV2 feature bits in ID_PFR0 register > arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register > arm64/cpufeature: Define an explicit ftr_id_isar0[] for ID_ISAR0 register > arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register > arm64/cpufeature: Replace all open bits shift encodings with macros > > arch/arm64/include/asm/cpu.h | 1 + > arch/arm64/include/asm/sysreg.h | 51 +++++++++++++++++++ > arch/arm64/kernel/cpufeature.c | 87 ++++++++++++++++++++++----------- > arch/arm64/kernel/cpuinfo.c | 1 + > arch/arm64/kvm/sys_regs.c | 2 +- > 5 files changed, 112 insertions(+), 30 deletions(-) >
On Fri, 14 Feb 2020 at 04:23, Anshuman Khandual <anshuman.khandual@arm.com> wrote: > > > > On 01/28/2020 06:09 PM, Anshuman Khandual wrote: > > This series is primarily motivated from an adhoc list from Mark Rutland > > during our ID_ISAR6 discussion [1]. Besides, it also includes a patch > > which does macro replacement for various open bits shift encodings in > > various CPU ID registers. This series is based on linux-next 20200124. > > > > [1] https://patchwork.kernel.org/patch/11287805/ > > > > Is there anything else apart from these changes which can be accommodated > > in this series, please do let me know. Thank you. > > Just a gentle ping. Any updates, does this series looks okay ? Is there > anything else related to CPU ID register feature bits, which can be added > up here. FWIW, the series still applies on v5.6-rc1. I just ran into some "32-bit KVM doesn't expose all the ID registers to userspace via the ONE_REG API" issues today. I don't know if they'd be reasonable as something to include in this patchset or if they're unrelated. Anyway, missing stuff I have noticed specifically: * MVFR2 * ID_MMFR4 * ID_ISAR6 More generally I would have expected all these 32-bit registers to exist and read-as-zero for the purpose of the ONE_REG APIs, because that's what the architecture says is supposed to happen and it means we have compatibility and QEMU doesn't gradually build up lots of "kernel doesn't support this yet" conditionals... I think we get this right for 64-bit KVM, but can we do it for 32-bit as well? thanks -- PMM
Hi Anshuman On 02/14/2020 04:23 AM, Anshuman Khandual wrote: > > > On 01/28/2020 06:09 PM, Anshuman Khandual wrote: >> This series is primarily motivated from an adhoc list from Mark Rutland >> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch >> which does macro replacement for various open bits shift encodings in >> various CPU ID registers. This series is based on linux-next 20200124. >> >> [1] https://patchwork.kernel.org/patch/11287805/ >> >> Is there anything else apart from these changes which can be accommodated >> in this series, please do let me know. Thank you. > > Just a gentle ping. Any updates, does this series looks okay ? Is there > anything else related to CPU ID register feature bits, which can be added > up here. FWIW, the series still applies on v5.6-rc1. Sorry for the delay ! The series looks good to me, except for some minor comments. Please see the individual patches. Cheers Suzuki
On 02/14/2020 09:28 PM, Peter Maydell wrote: > On Fri, 14 Feb 2020 at 04:23, Anshuman Khandual > <anshuman.khandual@arm.com> wrote: >> >> >> >> On 01/28/2020 06:09 PM, Anshuman Khandual wrote: >>> This series is primarily motivated from an adhoc list from Mark Rutland >>> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch >>> which does macro replacement for various open bits shift encodings in >>> various CPU ID registers. This series is based on linux-next 20200124. >>> >>> [1] https://patchwork.kernel.org/patch/11287805/ >>> >>> Is there anything else apart from these changes which can be accommodated >>> in this series, please do let me know. Thank you. >> >> Just a gentle ping. Any updates, does this series looks okay ? Is there >> anything else related to CPU ID register feature bits, which can be added >> up here. FWIW, the series still applies on v5.6-rc1. Sorry for the delay in response, was distracted on some other patches. > > I just ran into some "32-bit KVM doesn't expose all the ID > registers to userspace via the ONE_REG API" issues today. > I don't know if they'd be reasonable as something to include > in this patchset or if they're unrelated. IMHO, they are bit unrelated. > > Anyway, missing stuff I have noticed specifically: > * MVFR2 > * ID_MMFR4 > * ID_ISAR6 > > More generally I would have expected all these 32-bit registers > to exist and read-as-zero for the purpose of the ONE_REG APIs, > because that's what the architecture says is supposed to happen > and it means we have compatibility and QEMU doesn't gradually > build up lots of "kernel doesn't support this yet" conditionals... > I think we get this right for 64-bit KVM, but can we do it for > 32-bit as well? I am not very familiar with 32-bit KVM but will definitely keep these suggestions noted for later, also try and accommodate if possible. > thanks > -- PMM >
On Tue, Jan 28, 2020 at 06:09:03PM +0530, Anshuman Khandual wrote: > This series is primarily motivated from an adhoc list from Mark Rutland > during our ID_ISAR6 discussion [1]. Besides, it also includes a patch > which does macro replacement for various open bits shift encodings in > various CPU ID registers. This series is based on linux-next 20200124. > > [1] https://patchwork.kernel.org/patch/11287805/ > > Is there anything else apart from these changes which can be accommodated > in this series, please do let me know. Thank you. The latest Arm ARM also talks about DFR1 and MMFR5. Please can you include those too? Might also be worth checking to see if anything is missing on the 64-bit side as well (I didn't look). Will
On 04/06/2020 10:39 PM, Will Deacon wrote: > On Tue, Jan 28, 2020 at 06:09:03PM +0530, Anshuman Khandual wrote: >> This series is primarily motivated from an adhoc list from Mark Rutland >> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch >> which does macro replacement for various open bits shift encodings in >> various CPU ID registers. This series is based on linux-next 20200124. >> >> [1] https://patchwork.kernel.org/patch/11287805/ >> >> Is there anything else apart from these changes which can be accommodated >> in this series, please do let me know. Thank you. > > The latest Arm ARM also talks about DFR1 and MMFR5. Please can you include Sure, will do. > those too? Might also be worth checking to see if anything is missing on > the 64-bit side as well (I didn't look). Yeah. Now there some missing ones, will add those as well. > > Will >
On Tue, Apr 07, 2020 at 02:20:20PM +0530, Anshuman Khandual wrote: > > > On 04/06/2020 10:39 PM, Will Deacon wrote: > > On Tue, Jan 28, 2020 at 06:09:03PM +0530, Anshuman Khandual wrote: > >> This series is primarily motivated from an adhoc list from Mark Rutland > >> during our ID_ISAR6 discussion [1]. Besides, it also includes a patch > >> which does macro replacement for various open bits shift encodings in > >> various CPU ID registers. This series is based on linux-next 20200124. > >> > >> [1] https://patchwork.kernel.org/patch/11287805/ > >> > >> Is there anything else apart from these changes which can be accommodated > >> in this series, please do let me know. Thank you. > > > > The latest Arm ARM also talks about DFR1 and MMFR5. Please can you include > > Sure, will do. > > > those too? Might also be worth checking to see if anything is missing on > > the 64-bit side as well (I didn't look). > > Yeah. Now there some missing ones, will add those as well. Thanks. Just as a heads up that I've also got a handful of changes in this area, but we can resolve the conflicts at -rc1. https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git/log/?h=sanity-checks Will