[RFC,0/4] net: mfd: AC200 Ethernet PHY

Message

Jernej Škrabec April 16, 2020, 6:57 p.m. UTC

This is attempt to support Ethernet PHY on AC200 MFD chip. I'm sending
this as RFC because I stumbled on a problem how to properly describe it
in DT. Proper DT documentation will be added later, once DT issue is
solved.

Before Ethernet PHY can be actually used, few things must happen:
1. 24 MHz clock must be enabled and connected to input pin of this
   chip. In this case, PWM is set to generate 24 MHz signal with 50%
   duty cycle.
2. Chip must be put out of reset through I2C
3. Ethernet PHY must be enabled and configured through I2C

All above suggest that AC200 chip must be child node of I2C and Ethernet
PHY child node of AC200 node. This is done in patch 3.

However, mdio bus binding also requires that ethernet PHY is child node
of mdio bus node which can't be, because it's already child node of
AC200 MFD node.

Currently I'm using workaround to have another PHY defined in mdio bus
node as can be seen in patch 4. Then, with careful module loading order,
I make sure that ethernet controller driver is loaded last, after AC200
ethernet PHY driver is loaded. But that's fragile and not acceptable.

Suggestions how to solve that are highly appreciated.

One possible solution is that mdio bus node would contain phandle to
PHY node instead of having actual PHY child node.

Documentation of this chip can be found at
http://linux-sunxi.org/File:AC200_Datasheet_V1.1.pdf

Note that in this case, AC200 IC is copackaged with Allwinner H6 SoC and
all connections between them are internal. So, for example, PWM is the
only way to provide 24 MHz clock to this chip.

Best regards,
Jernej

Jernej Skrabec (4):
  mfd: Add support for AC200
  net: phy: Add support for AC200 EPHY
  arm64: dts: allwinner: h6: Add AC200 EPHY related nodes
  arm64: dts: allwinner: h6: tanix-tx6: Enable ethernet

 .../dts/allwinner/sun50i-h6-tanix-tx6.dts     |  32 +++
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |  63 ++++++
 drivers/mfd/Kconfig                           |   9 +
 drivers/mfd/Makefile                          |   1 +
 drivers/mfd/ac200.c                           | 188 ++++++++++++++++
 drivers/net/phy/Kconfig                       |   7 +
 drivers/net/phy/Makefile                      |   1 +
 drivers/net/phy/ac200.c                       | 206 +++++++++++++++++
 include/linux/mfd/ac200.h                     | 210 ++++++++++++++++++
 9 files changed, 717 insertions(+)
 create mode 100644 drivers/mfd/ac200.c
 create mode 100644 drivers/net/phy/ac200.c
 create mode 100644 include/linux/mfd/ac200.h

Comments

Andrew Lunn April 16, 2020, 9:54 p.m. UTC | #1

On Thu, Apr 16, 2020 at 08:57:54PM +0200, Jernej Skrabec wrote:
> This is attempt to support Ethernet PHY on AC200 MFD chip. I'm sending
> this as RFC because I stumbled on a problem how to properly describe it
> in DT. Proper DT documentation will be added later, once DT issue is
> solved.
> 
> Before Ethernet PHY can be actually used, few things must happen:
> 1. 24 MHz clock must be enabled and connected to input pin of this
>    chip. In this case, PWM is set to generate 24 MHz signal with 50%
>    duty cycle.
> 2. Chip must be put out of reset through I2C
> 3. Ethernet PHY must be enabled and configured through I2C

Hi Jernej

This is going to be interesting to describe in DT.

At what point does the PHY start responding to MDIO request? In
particular, you can read the ID registers 2 and 3? You list above what
is needed to make it usable. But we are also interested in what is
required to make is probe'able on the MDIO bus. We have more
flexibility if we can first probe it, and then later make it usable.

Thanks
	Andrew