diff mbox series

[v1,4/6] target/microblaze: Add the unaligned-exceptions property

Message ID 20200417191022.5247-5-edgar.iglesias@gmail.com (mailing list archive)
State New, archived
Headers show
Series target-microblaze: Misc configurability #2 | expand

Commit Message

Edgar E. Iglesias April 17, 2020, 7:10 p.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Add the unaligned-exceptions property to control if the core
traps unaligned memory accesses.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/cpu.c       | 4 ++++
 target/microblaze/cpu.h       | 1 +
 target/microblaze/translate.c | 4 ++--
 3 files changed, 7 insertions(+), 2 deletions(-)

Comments

Alistair Francis April 17, 2020, 9:35 p.m. UTC | #1 
On Fri, Apr 17, 2020 at 12:10 PM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Add the unaligned-exceptions property to control if the core
> traps unaligned memory accesses.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/microblaze/cpu.c       | 4 ++++
>  target/microblaze/cpu.h       | 1 +
>  target/microblaze/translate.c | 4 ++--
>  3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 7a40e2fbad..a850c7b23c 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -209,6 +209,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>                                                   PVR2_IOPB_BUS_EXC_MASK : 0) |
>                          (cpu->cfg.illegal_opcode_exception ?
>                                                  PVR2_ILL_OPCODE_EXC_MASK : 0) |
> +                        (cpu->cfg.unaligned_exceptions ?
> +                                                PVR2_UNALIGNED_EXC_MASK : 0) |
>                          (cpu->cfg.opcode_0_illegal ?
>                                                   PVR2_OPCODE_0x0_ILL_MASK : 0);
>
> @@ -282,6 +284,8 @@ static Property mb_properties[] = {
>                       cfg.illegal_opcode_exception, false),
>      DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
>                       cfg.div_zero_exception, false),
> +    DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
> +                     cfg.unaligned_exceptions, false),
>      DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
>                       cfg.opcode_0_illegal, false),
>      DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 3c07f9b3f7..ef9081db40 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -306,6 +306,7 @@ struct MicroBlazeCPU {
>          bool illegal_opcode_exception;
>          bool opcode_0_illegal;
>          bool div_zero_exception;
> +        bool unaligned_exceptions;
>          char *version;
>          uint8_t pvr;
>      } cfg;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index b4a78551ef..20b7427811 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -995,7 +995,7 @@ static void dec_load(DisasContext *dc)
>      v = tcg_temp_new_i32();
>      tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
>
> -    if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> +    if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
>          TCGv_i32 t0 = tcg_const_i32(0);
>          TCGv_i32 treg = tcg_const_i32(dc->rd);
>          TCGv_i32 tsize = tcg_const_i32(size - 1);
> @@ -1110,7 +1110,7 @@ static void dec_store(DisasContext *dc)
>      tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
>
>      /* Verify alignment if needed.  */
> -    if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> +    if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
>          TCGv_i32 t1 = tcg_const_i32(1);
>          TCGv_i32 treg = tcg_const_i32(dc->rd);
>          TCGv_i32 tsize = tcg_const_i32(size - 1);
> --
> 2.20.1
>
>
Luc Michel April 19, 2020, 7:26 p.m. UTC | #2 
On 4/17/20 9:10 PM, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
> 
> Add the unaligned-exceptions property to control if the core
> traps unaligned memory accesses.
> 
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>  target/microblaze/cpu.c       | 4 ++++
>  target/microblaze/cpu.h       | 1 +
>  target/microblaze/translate.c | 4 ++--
>  3 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
> index 7a40e2fbad..a850c7b23c 100644
> --- a/target/microblaze/cpu.c
> +++ b/target/microblaze/cpu.c
> @@ -209,6 +209,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
>                                                   PVR2_IOPB_BUS_EXC_MASK : 0) |
>                          (cpu->cfg.illegal_opcode_exception ?
>                                                  PVR2_ILL_OPCODE_EXC_MASK : 0) |
> +                        (cpu->cfg.unaligned_exceptions ?
> +                                                PVR2_UNALIGNED_EXC_MASK : 0) |
>                          (cpu->cfg.opcode_0_illegal ?
>                                                   PVR2_OPCODE_0x0_ILL_MASK : 0);
>  
> @@ -282,6 +284,8 @@ static Property mb_properties[] = {
>                       cfg.illegal_opcode_exception, false),
>      DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
>                       cfg.div_zero_exception, false),
> +    DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
> +                     cfg.unaligned_exceptions, false),
>      DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
>                       cfg.opcode_0_illegal, false),
>      DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
> diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
> index 3c07f9b3f7..ef9081db40 100644
> --- a/target/microblaze/cpu.h
> +++ b/target/microblaze/cpu.h
> @@ -306,6 +306,7 @@ struct MicroBlazeCPU {
>          bool illegal_opcode_exception;
>          bool opcode_0_illegal;
>          bool div_zero_exception;
> +        bool unaligned_exceptions;
>          char *version;
>          uint8_t pvr;
>      } cfg;
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index b4a78551ef..20b7427811 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -995,7 +995,7 @@ static void dec_load(DisasContext *dc)
>      v = tcg_temp_new_i32();
>      tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
>  
> -    if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> +    if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
>          TCGv_i32 t0 = tcg_const_i32(0);
>          TCGv_i32 treg = tcg_const_i32(dc->rd);
>          TCGv_i32 tsize = tcg_const_i32(size - 1);
> @@ -1110,7 +1110,7 @@ static void dec_store(DisasContext *dc)
>      tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
>  
>      /* Verify alignment if needed.  */
> -    if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
> +    if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
>          TCGv_i32 t1 = tcg_const_i32(1);
>          TCGv_i32 treg = tcg_const_i32(dc->rd);
>          TCGv_i32 tsize = tcg_const_i32(size - 1);
>
diff mbox series

Patch

diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
index 7a40e2fbad..a850c7b23c 100644
--- a/target/microblaze/cpu.c
+++ b/target/microblaze/cpu.c
@@ -209,6 +209,8 @@  static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
                                                  PVR2_IOPB_BUS_EXC_MASK : 0) |
                         (cpu->cfg.illegal_opcode_exception ?
                                                 PVR2_ILL_OPCODE_EXC_MASK : 0) |
+                        (cpu->cfg.unaligned_exceptions ?
+                                                PVR2_UNALIGNED_EXC_MASK : 0) |
                         (cpu->cfg.opcode_0_illegal ?
                                                  PVR2_OPCODE_0x0_ILL_MASK : 0);
 
@@ -282,6 +284,8 @@  static Property mb_properties[] = {
                      cfg.illegal_opcode_exception, false),
     DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
                      cfg.div_zero_exception, false),
+    DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
+                     cfg.unaligned_exceptions, false),
     DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
                      cfg.opcode_0_illegal, false),
     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 3c07f9b3f7..ef9081db40 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -306,6 +306,7 @@  struct MicroBlazeCPU {
         bool illegal_opcode_exception;
         bool opcode_0_illegal;
         bool div_zero_exception;
+        bool unaligned_exceptions;
         char *version;
         uint8_t pvr;
     } cfg;
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index b4a78551ef..20b7427811 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -995,7 +995,7 @@  static void dec_load(DisasContext *dc)
     v = tcg_temp_new_i32();
     tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
 
-    if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+    if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
         TCGv_i32 t0 = tcg_const_i32(0);
         TCGv_i32 treg = tcg_const_i32(dc->rd);
         TCGv_i32 tsize = tcg_const_i32(size - 1);
@@ -1110,7 +1110,7 @@  static void dec_store(DisasContext *dc)
     tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
 
     /* Verify alignment if needed.  */
-    if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
+    if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
         TCGv_i32 t1 = tcg_const_i32(1);
         TCGv_i32 treg = tcg_const_i32(dc->rd);
         TCGv_i32 tsize = tcg_const_i32(size - 1);