diff mbox series

[v3,9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers

Message ID 20200420190853.45614-10-kdasu.kdev@gmail.com (mailing list archive)
State New, archived
Headers show
Series [v3,1/9] spi: bcm-qspi: Handle clock probe deferral | expand

Commit Message

Kamal Dasu April 20, 2020, 7:08 p.m. UTC
Set MASTER bit on the MSPI_SPCR0_MSB only for legacy MSPI and HIF_MSPI
controllers.

Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver")
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
---
 drivers/spi/spi-bcm-qspi.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

Comments

Mark Brown April 21, 2020, 12:50 p.m. UTC | #1
On Mon, Apr 20, 2020 at 03:08:53PM -0400, Kamal Dasu wrote:
> Set MASTER bit on the MSPI_SPCR0_MSB only for legacy MSPI and HIF_MSPI
> controllers.
> 
> Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver")
> Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>

If this is a fix it should have been near the start of the series before
any new features to make sure that it can be applied cleanly as a fix.
Kamal Dasu April 21, 2020, 2:53 p.m. UTC | #2
On Tue, Apr 21, 2020 at 8:50 AM Mark Brown <broonie@kernel.org> wrote:
>
> On Mon, Apr 20, 2020 at 03:08:53PM -0400, Kamal Dasu wrote:
> > Set MASTER bit on the MSPI_SPCR0_MSB only for legacy MSPI and HIF_MSPI
> > controllers.
> >
> > Fixes: fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver")
> > Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
>
> If this is a fix it should have been near the start of the series before
> any new features to make sure that it can be applied cleanly as a fix.

Yes it could can be after [Patch v3 3/9] spi: bcm-qspi: Handle lack of
MSPI_REV offset

Kamal
Mark Brown April 21, 2020, 2:59 p.m. UTC | #3
On Tue, Apr 21, 2020 at 10:53:57AM -0400, Kamal Dasu wrote:
> On Tue, Apr 21, 2020 at 8:50 AM Mark Brown <broonie@kernel.org> wrote:

> > If this is a fix it should have been near the start of the series before
> > any new features to make sure that it can be applied cleanly as a fix.

> Yes it could can be after [Patch v3 3/9] spi: bcm-qspi: Handle lack of
> MSPI_REV offset

That's not a fix though, that's adding support for new devices?
Kamal Dasu April 21, 2020, 6:19 p.m. UTC | #4
On Tue, Apr 21, 2020 at 10:59 AM Mark Brown <broonie@kernel.org> wrote:
>
> On Tue, Apr 21, 2020 at 10:53:57AM -0400, Kamal Dasu wrote:
> > On Tue, Apr 21, 2020 at 8:50 AM Mark Brown <broonie@kernel.org> wrote:
>
> > > If this is a fix it should have been near the start of the series before
> > > any new features to make sure that it can be applied cleanly as a fix.
>
> > Yes it could can be after [Patch v3 3/9] spi: bcm-qspi: Handle lack of
> > MSPI_REV offset
>
> That's not a fix though, that's adding support for new devices?

Since its dependent on knowing if the MSPI_REV register exists on a
given SoC and path 3/9, maybe I can remove the fixes tag for that
commit.

Kamal

Kamal
diff mbox series

Patch

diff --git a/drivers/spi/spi-bcm-qspi.c b/drivers/spi/spi-bcm-qspi.c
index 99f2cfcbb50c..681d09085175 100644
--- a/drivers/spi/spi-bcm-qspi.c
+++ b/drivers/spi/spi-bcm-qspi.c
@@ -576,11 +576,17 @@  static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
 	spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
 
-	spcr = MSPI_MASTER_BIT;
+	if (!qspi->mspi_maj_rev)
+		/* legacy controller */
+		spcr = MSPI_MASTER_BIT;
+	else
+		spcr = 0;
+
 	/* for 16 bit the data should be zero */
 	if (xp->bits_per_word != 16)
 		spcr |= xp->bits_per_word << 2;
 	spcr |= xp->mode & 3;
+
 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
 
 	if (bcm_qspi_has_fastbr(qspi)) {