diff mbox series

[v4,1/2] clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150

Message ID 1586566362-21450-2-git-send-email-wcheng@codeaurora.org (mailing list archive)
State New, archived
Headers show
Series Enable SS/HS USB support on SM8150 | expand

Commit Message

Wesley Cheng April 11, 2020, 12:52 a.m. UTC 
This adds the USB3 PIPE clock and GDSC structures, so
that the USB driver can vote for these resources to be
enabled/disabled when required.  Both are needed for SS
and HS USB paths to operate properly.  The GDSC will
allow the USB system to be brought out of reset, while
the PIPE clock is needed for data transactions between
the PHY and controller.

Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
---
 drivers/clk/qcom/gcc-sm8150.c               | 52 +++++++++++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-sm8150.h |  4 +++
 2 files changed, 56 insertions(+)

Comments

Bjorn Andersson April 11, 2020, 1:01 a.m. UTC | #1 
On Fri 10 Apr 17:52 PDT 2020, Wesley Cheng wrote:

> This adds the USB3 PIPE clock and GDSC structures, so
> that the USB driver can vote for these resources to be
> enabled/disabled when required.  Both are needed for SS
> and HS USB paths to operate properly.  The GDSC will
> allow the USB system to be brought out of reset, while
> the PIPE clock is needed for data transactions between
> the PHY and controller.
> 
> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
> Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>


Stephen, let me know when you take this patch and I'll take the dts one.

Regards,
Bjorn

> ---
>  drivers/clk/qcom/gcc-sm8150.c               | 52 +++++++++++++++++++++++++++++
>  include/dt-bindings/clock/qcom,gcc-sm8150.h |  4 +++
>  2 files changed, 56 insertions(+)
> 
> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> index 2087721..ef98fdc 100644
> --- a/drivers/clk/qcom/gcc-sm8150.c
> +++ b/drivers/clk/qcom/gcc-sm8150.c
> @@ -21,6 +21,7 @@
>  #include "clk-rcg.h"
>  #include "clk-regmap.h"
>  #include "reset.h"
> +#include "gdsc.h"
>  
>  enum {
>  	P_BI_TCXO,
> @@ -3171,6 +3172,18 @@ enum {
>  	},
>  };
>  
> +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
> +	.halt_check = BRANCH_HALT_SKIP,
> +	.clkr = {
> +		.enable_reg = 0xf058,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_usb3_prim_phy_pipe_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
>  static struct clk_branch gcc_usb3_sec_clkref_clk = {
>  	.halt_reg = 0x8c028,
>  	.halt_check = BRANCH_HALT,
> @@ -3218,6 +3231,18 @@ enum {
>  	},
>  };
>  
> +static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
> +	.halt_check = BRANCH_HALT_SKIP,
> +	.clkr = {
> +		.enable_reg = 0x10058,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_usb3_sec_phy_pipe_clk",
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
>  /*
>   * Clock ON depends on external parent 'config noc', so cant poll
>   * delay and also mark as crtitical for video boot
> @@ -3292,6 +3317,24 @@ enum {
>  	},
>  };
>  
> +static struct gdsc usb30_prim_gdsc = {
> +		.gdscr = 0xf004,
> +		.pd = {
> +			.name = "usb30_prim_gdsc",
> +		},
> +		.pwrsts = PWRSTS_OFF_ON,
> +		.flags = POLL_CFG_GDSCR,
> +};
> +
> +static struct gdsc usb30_sec_gdsc = {
> +		.gdscr = 0x10004,
> +		.pd = {
> +			.name = "usb30_sec_gdsc",
> +		},
> +		.pwrsts = PWRSTS_OFF_ON,
> +		.flags = POLL_CFG_GDSCR,
> +};
> +
>  static struct clk_regmap *gcc_sm8150_clocks[] = {
>  	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
>  	[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
> @@ -3480,10 +3523,12 @@ enum {
>  	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
>  	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
>  	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
> +	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
>  	[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
>  	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
>  	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
>  	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
> +	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
>  	[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
>  	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
>  	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
> @@ -3527,6 +3572,11 @@ enum {
>  	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
>  };
>  
> +static struct gdsc *gcc_sm8150_gdscs[] = {
> +	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
> +	[USB30_SEC_GDSC] = &usb30_sec_gdsc,
> +};
> +
>  static const struct regmap_config gcc_sm8150_regmap_config = {
>  	.reg_bits	= 32,
>  	.reg_stride	= 4,
> @@ -3541,6 +3591,8 @@ enum {
>  	.num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
>  	.resets = gcc_sm8150_resets,
>  	.num_resets = ARRAY_SIZE(gcc_sm8150_resets),
> +	.gdscs = gcc_sm8150_gdscs,
> +	.num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
>  };
>  
>  static const struct of_device_id gcc_sm8150_match_table[] = {
> diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
> index 90d60ef..3e1a918 100644
> --- a/include/dt-bindings/clock/qcom,gcc-sm8150.h
> +++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
> @@ -240,4 +240,8 @@
>  #define GCC_USB30_SEC_BCR					27
>  #define GCC_USB_PHY_CFG_AHB2PHY_BCR				28
>  
> +/* GCC GDSCRs */
> +#define USB30_PRIM_GDSC                     4
> +#define USB30_SEC_GDSC						5
> +
>  #endif
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
Stephen Boyd April 22, 2020, 9:23 a.m. UTC | #2 
Quoting Bjorn Andersson (2020-04-10 18:01:43)
> On Fri 10 Apr 17:52 PDT 2020, Wesley Cheng wrote:
> 
> > This adds the USB3 PIPE clock and GDSC structures, so
> > that the USB driver can vote for these resources to be
> > enabled/disabled when required.  Both are needed for SS
> > and HS USB paths to operate properly.  The GDSC will
> > allow the USB system to be brought out of reset, while
> > the PIPE clock is needed for data transactions between
> > the PHY and controller.
> > 
> > Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
> > Reviewed-by: Stephen Boyd <sboyd@kernel.org>
> 
> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> 
> 
> Stephen, let me know when you take this patch and I'll take the dts one.
> 

Looks like I already applied it and it's merged in Linus' tree.
diff mbox series

Patch

diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 2087721..ef98fdc 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -21,6 +21,7 @@ 
 #include "clk-rcg.h"
 #include "clk-regmap.h"
 #include "reset.h"
+#include "gdsc.h"
 
 enum {
 	P_BI_TCXO,
@@ -3171,6 +3172,18 @@  enum {
 	},
 };
 
+static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
+	.halt_check = BRANCH_HALT_SKIP,
+	.clkr = {
+		.enable_reg = 0xf058,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_usb3_prim_phy_pipe_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 static struct clk_branch gcc_usb3_sec_clkref_clk = {
 	.halt_reg = 0x8c028,
 	.halt_check = BRANCH_HALT,
@@ -3218,6 +3231,18 @@  enum {
 	},
 };
 
+static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
+	.halt_check = BRANCH_HALT_SKIP,
+	.clkr = {
+		.enable_reg = 0x10058,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_usb3_sec_phy_pipe_clk",
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
 /*
  * Clock ON depends on external parent 'config noc', so cant poll
  * delay and also mark as crtitical for video boot
@@ -3292,6 +3317,24 @@  enum {
 	},
 };
 
+static struct gdsc usb30_prim_gdsc = {
+		.gdscr = 0xf004,
+		.pd = {
+			.name = "usb30_prim_gdsc",
+		},
+		.pwrsts = PWRSTS_OFF_ON,
+		.flags = POLL_CFG_GDSCR,
+};
+
+static struct gdsc usb30_sec_gdsc = {
+		.gdscr = 0x10004,
+		.pd = {
+			.name = "usb30_sec_gdsc",
+		},
+		.pwrsts = PWRSTS_OFF_ON,
+		.flags = POLL_CFG_GDSCR,
+};
+
 static struct clk_regmap *gcc_sm8150_clocks[] = {
 	[GCC_AGGRE_NOC_PCIE_TBU_CLK] = &gcc_aggre_noc_pcie_tbu_clk.clkr,
 	[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
@@ -3480,10 +3523,12 @@  enum {
 	[GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr,
 	[GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr,
 	[GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr,
+	[GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr,
 	[GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr,
 	[GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr,
 	[GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr,
 	[GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr,
+	[GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr,
 	[GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr,
 	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
 	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
@@ -3527,6 +3572,11 @@  enum {
 	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x6a000 },
 };
 
+static struct gdsc *gcc_sm8150_gdscs[] = {
+	[USB30_PRIM_GDSC] = &usb30_prim_gdsc,
+	[USB30_SEC_GDSC] = &usb30_sec_gdsc,
+};
+
 static const struct regmap_config gcc_sm8150_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
@@ -3541,6 +3591,8 @@  enum {
 	.num_clks = ARRAY_SIZE(gcc_sm8150_clocks),
 	.resets = gcc_sm8150_resets,
 	.num_resets = ARRAY_SIZE(gcc_sm8150_resets),
+	.gdscs = gcc_sm8150_gdscs,
+	.num_gdscs = ARRAY_SIZE(gcc_sm8150_gdscs),
 };
 
 static const struct of_device_id gcc_sm8150_match_table[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
index 90d60ef..3e1a918 100644
--- a/include/dt-bindings/clock/qcom,gcc-sm8150.h
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -240,4 +240,8 @@ 
 #define GCC_USB30_SEC_BCR					27
 #define GCC_USB_PHY_CFG_AHB2PHY_BCR				28
 
+/* GCC GDSCRs */
+#define USB30_PRIM_GDSC                     4
+#define USB30_SEC_GDSC						5
+
 #endif