| Message ID | 20200424044311.2155917-1-vkoul@kernel.org (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | [1/2] clk: qcom: gcc: Add GPU and NPU clocks for SM8150 | expand |
Quoting Vinod Koul (2020-04-23 21:43:10) > Add the GPU and NPU clocks for SM8150. They were missed in earlier > addition of clock driver. > > Signed-off-by: Vinod Koul <vkoul@kernel.org> Fixes tag? That way backporters know they're missing this. > --- > drivers/clk/qcom/gcc-sm8150.c | 72 +++++++++++++++++++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c > index ef98fdc51755..5c3dc34c955e 100644 > --- a/drivers/clk/qcom/gcc-sm8150.c > +++ b/drivers/clk/qcom/gcc-sm8150.c > @@ -1617,6 +1617,40 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { > }, > }; > > +/* external clocks so add BRANCH_HALT_SKIP */ > +static struct clk_branch gcc_gpu_gpll0_clk_src = { > + .halt_check = BRANCH_HALT_SKIP, > + .clkr = { > + .enable_reg = 0x52004, > + .enable_mask = BIT(15), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_gpu_gpll0_clk_src", > + .parent_hws = (const struct clk_hw *[]){ > + &gpll0.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +/* these are external clocks so add BRANCH_HALT_SKIP */ > +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { > + .halt_check = BRANCH_HALT_SKIP, > + .clkr = { > + .enable_reg = 0x52004, > + .enable_mask = BIT(16), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_gpu_gpll0_div_clk_src", > + .parent_hws = (const struct clk_hw *[]){ > + &gcc_gpu_gpll0_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_gpu_iref_clk = { > .halt_reg = 0x8c010, > .halt_check = BRANCH_HALT, > @@ -1699,6 +1733,40 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = { > }, > }; > > +/* external clocks so add BRANCH_HALT_SKIP */ > +static struct clk_branch gcc_npu_gpll0_clk_src = { > + .halt_check = BRANCH_HALT_SKIP, > + .clkr = { > + .enable_reg = 0x52004, > + .enable_mask = BIT(18), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_npu_gpll0_clk_src", > + .parent_hws = (const struct clk_hw *[]){ > + &gpll0.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +/* external clocks so add BRANCH_HALT_SKIP */ None of these look external. The parents are all inside this driver. Why are we skipping the halt check? > +static struct clk_branch gcc_npu_gpll0_div_clk_src = { > + .halt_check = BRANCH_HALT_SKIP, > + .clkr = { > + .enable_reg = 0x52004, > + .enable_mask = BIT(19), > + .hw.init = &(struct clk_init_data){ > + .name = "gcc_npu_gpll0_div_clk_src", > + .parent_hws = (const struct clk_hw *[]){ > + &gcc_npu_gpll0_clk_src.clkr.hw }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > static struct clk_branch gcc_npu_trig_clk = { > .halt_reg = 0x4d00c, > .halt_check = BRANCH_VOTED,
On 25-04-20, 12:10, Stephen Boyd wrote: > Quoting Vinod Koul (2020-04-23 21:43:10) > > Add the GPU and NPU clocks for SM8150. They were missed in earlier > > addition of clock driver. > > > > Signed-off-by: Vinod Koul <vkoul@kernel.org> > > Fixes tag? That way backporters know they're missing this. Yes it makes sense to add here, will add. > > +/* external clocks so add BRANCH_HALT_SKIP */ > > +static struct clk_branch gcc_npu_gpll0_clk_src = { > > + .halt_check = BRANCH_HALT_SKIP, > > + .clkr = { > > + .enable_reg = 0x52004, > > + .enable_mask = BIT(18), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gcc_npu_gpll0_clk_src", > > + .parent_hws = (const struct clk_hw *[]){ > > + &gpll0.clkr.hw }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +/* external clocks so add BRANCH_HALT_SKIP */ > > None of these look external. The parents are all inside this driver. Why > are we skipping the halt check? yeah not sure why this got added here, tested and these look fine. I will update these and send update. Thanks for the review
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c index ef98fdc51755..5c3dc34c955e 100644 --- a/drivers/clk/qcom/gcc-sm8150.c +++ b/drivers/clk/qcom/gcc-sm8150.c @@ -1617,6 +1617,40 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { }, }; +/* external clocks so add BRANCH_HALT_SKIP */ +static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &gpll0.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +/* these are external clocks so add BRANCH_HALT_SKIP */ +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(16), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &gcc_gpu_gpll0_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_gpu_iref_clk = { .halt_reg = 0x8c010, .halt_check = BRANCH_HALT, @@ -1699,6 +1733,40 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = { }, }; +/* external clocks so add BRANCH_HALT_SKIP */ +static struct clk_branch gcc_npu_gpll0_clk_src = { + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(18), + .hw.init = &(struct clk_init_data){ + .name = "gcc_npu_gpll0_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &gpll0.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +/* external clocks so add BRANCH_HALT_SKIP */ +static struct clk_branch gcc_npu_gpll0_div_clk_src = { + .halt_check = BRANCH_HALT_SKIP, + .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(19), + .hw.init = &(struct clk_init_data){ + .name = "gcc_npu_gpll0_div_clk_src", + .parent_hws = (const struct clk_hw *[]){ + &gcc_npu_gpll0_clk_src.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + static struct clk_branch gcc_npu_trig_clk = { .halt_reg = 0x4d00c, .halt_check = BRANCH_VOTED, @@ -3375,12 +3443,16 @@ static struct clk_regmap *gcc_sm8150_clocks[] = { [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, + [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr, [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, + [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, + [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr, [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
Add the GPU and NPU clocks for SM8150. They were missed in earlier addition of clock driver. Signed-off-by: Vinod Koul <vkoul@kernel.org> --- drivers/clk/qcom/gcc-sm8150.c | 72 +++++++++++++++++++++++++++++++++++ 1 file changed, 72 insertions(+)