Message ID | 20200426121709.1216-1-peron.clem@gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | arm64: dts: allwinner: h6: Use dedicated CPU OPP table for Tanix TX6 | expand |
Hi Warpme, On Sun, 26 Apr 2020 at 14:17, Clément Péron <peron.clem@gmail.com> wrote: > > Tanix TX6 has a fixed regulator. As DVFS is instructed to change > voltage to meet OPP table. The DVFS is not working as expected. > > Introduce a dedicated OPP Table where voltage are equals to > the fixed regulator. > > Reported-by: Piotr Oniszczuk <warpme@o2.pl> > Fixes: add1e27fb703 ("arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6") > Signed-off-by: Clément Péron <peron.clem@gmail.com> Could you confirm this patch fixed your issue? If yes could you add your tested-by tag ? Thanks, Clement > --- > .../sun50i-h6-tanix-tx6-cpu-opp.dtsi | 116 ++++++++++++++++++ > .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 2 +- > 2 files changed, 117 insertions(+), 1 deletion(-) > create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-cpu-opp.dtsi > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-cpu-opp.dtsi > new file mode 100644 > index 000000000000..062940115563 > --- /dev/null > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-cpu-opp.dtsi > @@ -0,0 +1,116 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com> > + > +/ { > + cpu_opp_table: cpu-opp-table { > + compatible = "allwinner,sun50i-h6-operating-points"; > + nvmem-cells = <&cpu_speed_grade>; > + opp-shared; > + > + opp@480000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-hz = /bits/ 64 <480000000>; > + > + opp-microvolt-speed0 = <1135000>; > + opp-microvolt-speed1 = <1135000>; > + opp-microvolt-speed2 = <1135000>; > + }; > + > + opp@720000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-hz = /bits/ 64 <720000000>; > + > + opp-microvolt-speed0 = <1135000>; > + opp-microvolt-speed1 = <1135000>; > + opp-microvolt-speed2 = <1135000>; > + }; > + > + opp@816000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-hz = /bits/ 64 <816000000>; > + > + opp-microvolt-speed0 = <1135000>; > + opp-microvolt-speed1 = <1135000>; > + opp-microvolt-speed2 = <1135000>; > + }; > + > + opp@888000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-hz = /bits/ 64 <888000000>; > + > + opp-microvolt-speed0 = <1135000>; > + opp-microvolt-speed1 = <1135000>; > + opp-microvolt-speed2 = <1135000>; > + }; > + > + opp@1080000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-hz = /bits/ 64 <1080000000>; > + > + opp-microvolt-speed0 = <1135000>; > + opp-microvolt-speed1 = <1135000>; > + opp-microvolt-speed2 = <1135000>; > + }; > + > + opp@1320000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-hz = /bits/ 64 <1320000000>; > + > + opp-microvolt-speed0 = <1135000>; > + opp-microvolt-speed1 = <1135000>; > + opp-microvolt-speed2 = <1135000>; > + }; > + > + opp@1488000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-hz = /bits/ 64 <1488000000>; > + > + opp-microvolt-speed0 = <1135000>; > + opp-microvolt-speed1 = <1135000>; > + opp-microvolt-speed2 = <1135000>; > + }; > + > + opp@1608000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-hz = /bits/ 64 <1608000000>; > + > + opp-microvolt-speed0 = <1135000>; > + opp-microvolt-speed1 = <1135000>; > + opp-microvolt-speed2 = <1135000>; > + }; > + > + opp@1704000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-hz = /bits/ 64 <1704000000>; > + > + opp-microvolt-speed0 = <1135000>; > + opp-microvolt-speed1 = <1135000>; > + opp-microvolt-speed2 = <1135000>; > + }; > + > + opp@1800000000 { > + clock-latency-ns = <244144>; /* 8 32k periods */ > + opp-hz = /bits/ 64 <1800000000>; > + > + opp-microvolt-speed0 = <1135000>; > + opp-microvolt-speed1 = <1135000>; > + opp-microvolt-speed2 = <1135000>; > + }; > + }; > +}; > + > +&cpu0 { > + operating-points-v2 = <&cpu_opp_table>; > +}; > + > +&cpu1 { > + operating-points-v2 = <&cpu_opp_table>; > +}; > + > +&cpu2 { > + operating-points-v2 = <&cpu_opp_table>; > +}; > + > +&cpu3 { > + operating-points-v2 = <&cpu_opp_table>; > +}; > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts > index be81330db14f..3eaa4f49e3d3 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts > @@ -4,7 +4,7 @@ > /dts-v1/; > > #include "sun50i-h6.dtsi" > -#include "sun50i-h6-cpu-opp.dtsi" > +#inlcude "sun50i-h6-tanix-tx6-cpu-opp.dtsi" > > #include <dt-bindings/gpio/gpio.h> > > -- > 2.20.1 >
On Sun, Apr 26, 2020 at 02:17:09PM +0200, Clément Péron wrote: > Tanix TX6 has a fixed regulator. As DVFS is instructed to change > voltage to meet OPP table. The DVFS is not working as expected. > > Introduce a dedicated OPP Table where voltage are equals to > the fixed regulator. > > Reported-by: Piotr Oniszczuk <warpme@o2.pl> > Fixes: add1e27fb703 ("arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6") > Signed-off-by: Clément Péron <peron.clem@gmail.com> I'm not really a big fan of duplicating the OPPs, since that would make an update of those very likely to be overlooked for that particular board (and since it's a board that not a lot of people have, it would be harder to notice too). IIRC, removing the cpu-supply property should work as well? Maxime
Hi Maxime, On Tue, 28 Apr 2020 at 09:52, Maxime Ripard <maxime@cerno.tech> wrote: > > On Sun, Apr 26, 2020 at 02:17:09PM +0200, Clément Péron wrote: > > Tanix TX6 has a fixed regulator. As DVFS is instructed to change > > voltage to meet OPP table. The DVFS is not working as expected. > > > > Introduce a dedicated OPP Table where voltage are equals to > > the fixed regulator. > > > > Reported-by: Piotr Oniszczuk <warpme@o2.pl> > > Fixes: add1e27fb703 ("arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6") > > Signed-off-by: Clément Péron <peron.clem@gmail.com> > > I'm not really a big fan of duplicating the OPPs, since that would make an > update of those very likely to be overlooked for that particular board (and > since it's a board that not a lot of people have, it would be harder to notice > too). > > IIRC, removing the cpu-supply property should work as well? Yes it would works also the OPP will provide a dummy regulator. But as it has been introduced and there is a cpu regulator in the real life. I thought it was a bit a hack to just remove it but as you wish. Regards, Clement > > Maxime
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-cpu-opp.dtsi new file mode 100644 index 000000000000..062940115563 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-cpu-opp.dtsi @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com> + +/ { + cpu_opp_table: cpu-opp-table { + compatible = "allwinner,sun50i-h6-operating-points"; + nvmem-cells = <&cpu_speed_grade>; + opp-shared; + + opp@480000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <480000000>; + + opp-microvolt-speed0 = <1135000>; + opp-microvolt-speed1 = <1135000>; + opp-microvolt-speed2 = <1135000>; + }; + + opp@720000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <720000000>; + + opp-microvolt-speed0 = <1135000>; + opp-microvolt-speed1 = <1135000>; + opp-microvolt-speed2 = <1135000>; + }; + + opp@816000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <816000000>; + + opp-microvolt-speed0 = <1135000>; + opp-microvolt-speed1 = <1135000>; + opp-microvolt-speed2 = <1135000>; + }; + + opp@888000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <888000000>; + + opp-microvolt-speed0 = <1135000>; + opp-microvolt-speed1 = <1135000>; + opp-microvolt-speed2 = <1135000>; + }; + + opp@1080000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1080000000>; + + opp-microvolt-speed0 = <1135000>; + opp-microvolt-speed1 = <1135000>; + opp-microvolt-speed2 = <1135000>; + }; + + opp@1320000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1320000000>; + + opp-microvolt-speed0 = <1135000>; + opp-microvolt-speed1 = <1135000>; + opp-microvolt-speed2 = <1135000>; + }; + + opp@1488000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1488000000>; + + opp-microvolt-speed0 = <1135000>; + opp-microvolt-speed1 = <1135000>; + opp-microvolt-speed2 = <1135000>; + }; + + opp@1608000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1608000000>; + + opp-microvolt-speed0 = <1135000>; + opp-microvolt-speed1 = <1135000>; + opp-microvolt-speed2 = <1135000>; + }; + + opp@1704000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1704000000>; + + opp-microvolt-speed0 = <1135000>; + opp-microvolt-speed1 = <1135000>; + opp-microvolt-speed2 = <1135000>; + }; + + opp@1800000000 { + clock-latency-ns = <244144>; /* 8 32k periods */ + opp-hz = /bits/ 64 <1800000000>; + + opp-microvolt-speed0 = <1135000>; + opp-microvolt-speed1 = <1135000>; + opp-microvolt-speed2 = <1135000>; + }; + }; +}; + +&cpu0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&cpu3 { + operating-points-v2 = <&cpu_opp_table>; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts index be81330db14f..3eaa4f49e3d3 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts @@ -4,7 +4,7 @@ /dts-v1/; #include "sun50i-h6.dtsi" -#include "sun50i-h6-cpu-opp.dtsi" +#inlcude "sun50i-h6-tanix-tx6-cpu-opp.dtsi" #include <dt-bindings/gpio/gpio.h>
Tanix TX6 has a fixed regulator. As DVFS is instructed to change voltage to meet OPP table. The DVFS is not working as expected. Introduce a dedicated OPP Table where voltage are equals to the fixed regulator. Reported-by: Piotr Oniszczuk <warpme@o2.pl> Fixes: add1e27fb703 ("arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6") Signed-off-by: Clément Péron <peron.clem@gmail.com> --- .../sun50i-h6-tanix-tx6-cpu-opp.dtsi | 116 ++++++++++++++++++ .../dts/allwinner/sun50i-h6-tanix-tx6.dts | 2 +- 2 files changed, 117 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-cpu-opp.dtsi