| Message ID | 1588197415-13747-10-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | Add R8A7742/RZG1H board support | expand |
On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Describe the IRQC interrupt controller in the r8a7742 device tree. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Gr{oetje,eeting}s, Geert
On 2020-04-30 14:54, Geert Uytterhoeven wrote: > On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: >> Describe the IRQC interrupt controller in the r8a7742 device tree. >> >> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> >> Reviewed-by: Marian-Cristian Rotariu >> <marian-cristian.rotariu.rb@bp.renesas.com> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Can I safely assume that the irqchip DT updates will be routed via the arm-soc tree? If so, feel free to add my Acked-by: Marc Zyngier <maz@kernel.org> to these patches. Thanks, M.
Hi Marc, On Thu, Apr 30, 2020 at 4:01 PM Marc Zyngier <maz@kernel.org> wrote: > On 2020-04-30 14:54, Geert Uytterhoeven wrote: > > On Wed, Apr 29, 2020 at 11:58 PM Lad Prabhakar > > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > >> Describe the IRQC interrupt controller in the r8a7742 device tree. > >> > >> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > >> Reviewed-by: Marian-Cristian Rotariu > >> <marian-cristian.rotariu.rb@bp.renesas.com> > > > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Can I safely assume that the irqchip DT updates will be routed via > the arm-soc tree? If so, feel free to add my Yes they will, eventually. > Acked-by: Marc Zyngier <maz@kernel.org> > > to these patches. Thanks! Gr{oetje,eeting}s, Geert
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index a2c858e..4c7baf2 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -337,6 +337,20 @@ #power-domain-cells = <1>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7742", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7742_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>;