Message ID | 20200504124752.29806-1-andrew.cooper3@citrix.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | x86/ucode/intel: Writeback and invalidate caches before updating microcode | expand |
On 04.05.2020 14:47, Andrew Cooper wrote: > From: Ashok Raj <ashok.raj@intel.com> > > Updating microcode is less error prone when caches have been flushed and > depending on what exactly the microcode is updating. For example, some of the > issues around certain Broadwell parts can be addressed by doing a full cache > flush. > > Signed-off-by: Ashok Raj <ashok.raj@intel.com> > Signed-off-by: Borislav Petkov <bp@suse.de> > Signed-off-by: Thomas Gleixner <tglx@linutronix.de> > [Linux commit 91df9fdf51492aec9fed6b4cbd33160886740f47, ported to Xen] > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> Acked-by: Jan Beulich <jbeulich@suse.com>
diff --git a/xen/arch/x86/cpu/microcode/intel.c b/xen/arch/x86/cpu/microcode/intel.c index a9f4d6e829..d031196d4c 100644 --- a/xen/arch/x86/cpu/microcode/intel.c +++ b/xen/arch/x86/cpu/microcode/intel.c @@ -25,6 +25,7 @@ #include <xen/init.h> #include <asm/msr.h> +#include <asm/system.h> #include "private.h" @@ -267,6 +268,8 @@ static int apply_microcode(const struct microcode_patch *patch) if ( microcode_update_match(patch) != NEW_UCODE ) return -EINVAL; + wbinvd(); + /* write microcode via MSR 0x79 */ wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)patch->data); wrmsrl(MSR_IA32_UCODE_REV, 0x0ULL);