Message ID | 20200502043234.12481-1-sean.j.christopherson@intel.com (mailing list archive) |
---|---|
Headers | show |
Series | KVM: x86: Misc anti-retpoline optimizations | expand |
On 02/05/20 06:32, Sean Christopherson wrote: > A smattering of optimizations geared toward avoiding retpolines, though > IMO most of the patches are worthwhile changes irrespective of retpolines. > I can split this up into separate patches if desired, outside of the > obvious combos there are no dependencies. Most of them are good stuff anyway, I agree. Since I like to believe that static calls _are_ close, I queued these: KVM: x86: Save L1 TSC offset in 'struct kvm_vcpu_arch' KVM: nVMX: Unconditionally validate CR3 during nested transitions KVM: VMX: Add proper cache tracking for CR4 KVM: VMX: Add proper cache tracking for CR0 KVM: VMX: Move nested EPT out of kvm_x86_ops.get_tdp_level() hook KVM: x86/mmu: Capture TDP level when updating CPUID and I don't disagree with the DR6 one though it can be even improved a bit so I'll send a patch myself. Paolo
On Mon, May 04, 2020 at 03:25:58PM +0200, Paolo Bonzini wrote: > On 02/05/20 06:32, Sean Christopherson wrote: > > A smattering of optimizations geared toward avoiding retpolines, though > > IMO most of the patches are worthwhile changes irrespective of retpolines. > > I can split this up into separate patches if desired, outside of the > > obvious combos there are no dependencies. > > Most of them are good stuff anyway, I agree. > > Since I like to believe that static calls _are_ close, I queued these: > > KVM: x86: Save L1 TSC offset in 'struct kvm_vcpu_arch' > KVM: nVMX: Unconditionally validate CR3 during nested transitions > KVM: VMX: Add proper cache tracking for CR4 > KVM: VMX: Add proper cache tracking for CR0 > KVM: VMX: Move nested EPT out of kvm_x86_ops.get_tdp_level() hook > KVM: x86/mmu: Capture TDP level when updating CPUID > > and I don't disagree with the DR6 one though it can be even improved a > bit so I'll send a patch myself. Sounds good, thanks!