| Message ID | 20200430143424.2787566-2-jean-philippe@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | iommu: Shared Virtual Addressing for SMMUv3 | expand |
On 2020/4/30 22:34, Jean-Philippe Brucker wrote: > Some devices can tag their DMA requests with a 20-bit Process Address > Space ID (PASID), allowing them to access multiple address spaces. In > combination with recoverable I/O page faults (for example PCIe PRI), > PASID allows the IOMMU to share page tables with the MMU. > > To make sure that a single PASID is allocated for each address space, as > required by Intel ENQCMD, store the PASID in the mm_struct. The IOMMU > driver is in charge of serializing modifications to the PASID field. > > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> > --- > For the field's validity I'm thinking invalid PASID = 0. In ioasid.h we > define INVALID_IOASID as ~0U, but I think we can now change it to 0, > since Intel is now also reserving PASID #0 for Transactions without > PASID and AMD IOMMU uses GIoV for this too. > --- > include/linux/mm_types.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h > index 4aba6c0c2ba80..8db6472758175 100644 > --- a/include/linux/mm_types.h > +++ b/include/linux/mm_types.h > @@ -534,6 +534,10 @@ struct mm_struct { > atomic_long_t hugetlb_usage; > #endif > struct work_struct async_put_work; > +#ifdef CONFIG_IOMMU_SUPPORT > + /* Address space ID used by device DMA */ > + unsigned int pasid; > +#endif Maybe '#ifdef CONFIG_IOMMU_SVA ... #endif' is more reasonable? Thanks, Zaibo . > } __randomize_layout; > > /*
On Mon, May 04, 2020 at 09:52:44AM +0800, Xu Zaibo wrote: > > On 2020/4/30 22:34, Jean-Philippe Brucker wrote: > > Some devices can tag their DMA requests with a 20-bit Process Address > > Space ID (PASID), allowing them to access multiple address spaces. In > > combination with recoverable I/O page faults (for example PCIe PRI), > > PASID allows the IOMMU to share page tables with the MMU. > > > > To make sure that a single PASID is allocated for each address space, as > > required by Intel ENQCMD, store the PASID in the mm_struct. The IOMMU > > driver is in charge of serializing modifications to the PASID field. > > > > Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> > > --- > > For the field's validity I'm thinking invalid PASID = 0. In ioasid.h we > > define INVALID_IOASID as ~0U, but I think we can now change it to 0, > > since Intel is now also reserving PASID #0 for Transactions without > > PASID and AMD IOMMU uses GIoV for this too. > > --- > > include/linux/mm_types.h | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h > > index 4aba6c0c2ba80..8db6472758175 100644 > > --- a/include/linux/mm_types.h > > +++ b/include/linux/mm_types.h > > @@ -534,6 +534,10 @@ struct mm_struct { > > atomic_long_t hugetlb_usage; > > #endif > > struct work_struct async_put_work; > > +#ifdef CONFIG_IOMMU_SUPPORT > > + /* Address space ID used by device DMA */ > > + unsigned int pasid; > > +#endif > Maybe '#ifdef CONFIG_IOMMU_SVA ... #endif' is more reasonable? CONFIG_IOMMU_SVA enables a few helpers but IOMMU drivers don't have to use them, so I think IOMMU_SUPPORT is more appropriate. Thanks, Jean
diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h index 4aba6c0c2ba80..8db6472758175 100644 --- a/include/linux/mm_types.h +++ b/include/linux/mm_types.h @@ -534,6 +534,10 @@ struct mm_struct { atomic_long_t hugetlb_usage; #endif struct work_struct async_put_work; +#ifdef CONFIG_IOMMU_SUPPORT + /* Address space ID used by device DMA */ + unsigned int pasid; +#endif } __randomize_layout; /*
Some devices can tag their DMA requests with a 20-bit Process Address Space ID (PASID), allowing them to access multiple address spaces. In combination with recoverable I/O page faults (for example PCIe PRI), PASID allows the IOMMU to share page tables with the MMU. To make sure that a single PASID is allocated for each address space, as required by Intel ENQCMD, store the PASID in the mm_struct. The IOMMU driver is in charge of serializing modifications to the PASID field. Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org> --- For the field's validity I'm thinking invalid PASID = 0. In ioasid.h we define INVALID_IOASID as ~0U, but I think we can now change it to 0, since Intel is now also reserving PASID #0 for Transactions without PASID and AMD IOMMU uses GIoV for this too. --- include/linux/mm_types.h | 4 ++++ 1 file changed, 4 insertions(+)