diff mbox series

[v2,07/20] mips: Add MIPS Warrior P5600 support

Message ID 20200506174238.15385-8-Sergey.Semin@baikalelectronics.ru (mailing list archive)
State Superseded
Headers show
Series None | expand

Commit Message

Serge Semin May 6, 2020, 5:42 p.m. UTC 
From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

This is a MIPS32 Release 5 based IP core with XPA, EVA, dual/quad issue
exec pipes, MMU with two-levels TLB, UCA, MSA, MDU core level features
and system level features like up to six P5600 calculation cores, CM2
with L2 cache, IOCU/IOMMU (though might be unused depending on the
system-specific IP core configuration), GIC, CPC, virtualisation module,
eJTAG and PDtrace.

As being MIPS32 Release 5 based core it provides all the features
available by the CPU_MIPS32_R5 config, while adding a few more like
UCA attribute support, availability of CPU-freq (by means of L2/CM
clock ratio setting), EI/VI GIC modes detection at runtime.

In addition to this if P5600 architecture is enabled modern GNU GCC
provides a specific tuning for P5600 processors with respect to the
classic MIPS32 Release 5. First of all branch-likely avoidance is
activated only when the code is compiled with the speed optimization
(avoidance is always enabled for the pure MIPS32 Release 5
architecture). Secondly the madd/msub avoidance is enabled since
madd/msub utilization isn't profitable due to overhead of getting the
result out of the HI/LO registers. Multiply-accumulate instructions are
activated and utilized together with the necessary code reorder when
multiply-add/multiply-subtract statements are met. Finally load/store
bonding is activated by default. All of these optimizations may make
the code relatively faster than if just MIP32 release 5 architecture
was requested.

Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-pm@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
 arch/mips/Kconfig                | 38 +++++++++++++++++++++++++++-----
 arch/mips/Makefile               |  1 +
 arch/mips/include/asm/vermagic.h |  2 ++
 3 files changed, 36 insertions(+), 5 deletions(-)

Comments

Thomas Bogendoerfer May 7, 2020, 11:17 a.m. UTC | #1 
On Wed, May 06, 2020 at 08:42:25PM +0300, Sergey.Semin@baikalelectronics.ru wrote:
>  
> +config CPU_P5600
> +	bool "MIPS Warrior P5600"
> +	depends on SYS_HAS_CPU_P5600
> +	select CPU_HAS_PREFETCH
> +	select CPU_SUPPORTS_32BIT_KERNEL
> +	select CPU_SUPPORTS_HIGHMEM
> +	select CPU_SUPPORTS_MSA
> +	select CPU_SUPPORTS_UNCACHED_ACCELERATED
> +	select CPU_SUPPORTS_CPUFREQ
> +	select CPU_MIPSR2_IRQ_VI
> +	select CPU_MIPSR2_IRQ_EI
> +	select HAVE_KVM
> +	select MIPS_O32_FP64_SUPPORT
> +	help
> +	  Choose this option to build a kernel for MIPS Warrior P5600 CPU.
> +	  It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
> +	  MMU with two-levels TLB, UCA, MSA, MDU core level features and system
> +	  level features like up to six P5600 calculation cores, CM2 with L2
> +	  cache, IOCU/IOMMU (though might be unused depending on the system-
> +	  specific IP core configuration), GIC, CPC, virtualisation module,
> +	  eJTAG and PDtrace.
> +
>  config CPU_R3000
>  	bool "R3000"
>  	depends on SYS_HAS_CPU_R3000
> @@ -1841,7 +1863,8 @@ endchoice
>  config CPU_MIPS32_3_5_FEATURES
>  	bool "MIPS32 Release 3.5 Features"
>  	depends on SYS_HAS_CPU_MIPS32_R3_5
> -	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6
> +	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
> +		   CPU_P5600
>  	help
>  	  Choose this option to build a kernel for release 2 or later of the
>  	  MIPS32 architecture including features from the 3.5 release such as
> @@ -1861,7 +1884,7 @@ config CPU_MIPS32_3_5_EVA
>  config CPU_MIPS32_R5_FEATURES
>  	bool "MIPS32 Release 5 Features"
>  	depends on SYS_HAS_CPU_MIPS32_R5
> -	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5
> +	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
>  	help
>  	  Choose this option to build a kernel for release 2 or later of the
>  	  MIPS32 architecture including features from release 5 such as
> @@ -2016,6 +2039,10 @@ config SYS_HAS_CPU_MIPS64_R6
>  	bool
>  	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
>  
> +config SYS_HAS_CPU_P5600
> +	bool
> +	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
> +

P5600 is CPU_MIPS_R5 so can't you select it here and drop all the || CPU_5600
above/below ?

Thomas.
Serge Semin May 7, 2020, 9:19 p.m. UTC | #2 
On Thu, May 07, 2020 at 01:17:35PM +0200, Thomas Bogendoerfer wrote:
> On Wed, May 06, 2020 at 08:42:25PM +0300, Sergey.Semin@baikalelectronics.ru wrote:
> >  
> > +config CPU_P5600
> > +	bool "MIPS Warrior P5600"
> > +	depends on SYS_HAS_CPU_P5600
> > +	select CPU_HAS_PREFETCH
> > +	select CPU_SUPPORTS_32BIT_KERNEL
> > +	select CPU_SUPPORTS_HIGHMEM
> > +	select CPU_SUPPORTS_MSA
> > +	select CPU_SUPPORTS_UNCACHED_ACCELERATED
> > +	select CPU_SUPPORTS_CPUFREQ
> > +	select CPU_MIPSR2_IRQ_VI
> > +	select CPU_MIPSR2_IRQ_EI
> > +	select HAVE_KVM
> > +	select MIPS_O32_FP64_SUPPORT
> > +	help
> > +	  Choose this option to build a kernel for MIPS Warrior P5600 CPU.
> > +	  It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
> > +	  MMU with two-levels TLB, UCA, MSA, MDU core level features and system
> > +	  level features like up to six P5600 calculation cores, CM2 with L2
> > +	  cache, IOCU/IOMMU (though might be unused depending on the system-
> > +	  specific IP core configuration), GIC, CPC, virtualisation module,
> > +	  eJTAG and PDtrace.
> > +
> >  config CPU_R3000
> >  	bool "R3000"
> >  	depends on SYS_HAS_CPU_R3000
> > @@ -1841,7 +1863,8 @@ endchoice
> >  config CPU_MIPS32_3_5_FEATURES
> >  	bool "MIPS32 Release 3.5 Features"
> >  	depends on SYS_HAS_CPU_MIPS32_R3_5
> > -	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6
> > +	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
> > +		   CPU_P5600
> >  	help
> >  	  Choose this option to build a kernel for release 2 or later of the
> >  	  MIPS32 architecture including features from the 3.5 release such as
> > @@ -1861,7 +1884,7 @@ config CPU_MIPS32_3_5_EVA
> >  config CPU_MIPS32_R5_FEATURES
> >  	bool "MIPS32 Release 5 Features"
> >  	depends on SYS_HAS_CPU_MIPS32_R5
> > -	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5
> > +	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
> >  	help
> >  	  Choose this option to build a kernel for release 2 or later of the
> >  	  MIPS32 architecture including features from release 5 such as
> > @@ -2016,6 +2039,10 @@ config SYS_HAS_CPU_MIPS64_R6
> >  	bool
> >  	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
> >  
> > +config SYS_HAS_CPU_P5600
> > +	bool
> > +	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
> > +
> 
> P5600 is CPU_MIPS_R5 so can't you select it here and drop all the || CPU_5600
> above/below ?

Alas, We can't do this so easy. CONFIG_CPU_MIPS32_{R2,R5,R6} and any other
CONFIG_CPU_* configs is something that kernel config-file is supposed to select.
Their availability is enabled by the CONFIG_SYS_HAS_CPU_* configs. CONFIG_CPU_*
is supposed to activate CPU-specific features and there is only one
CONFIG_CPU_x can be enabled at a time seeing it's a part of the "CPU type"
choice kconfig menu. In addition the CPU config also tunes a compiler to activate
the arch-specific ISA and optimizations in the arch/mips/Makefile by setting
-march=cpu-name (where cpu-name can be p5600, mips32r5, etc).

Yes, P5600 is based on the MIPS32r5, but it also has got some specific features
(see config CPU_P5600 and config MIPS32_R5), which makes it to be different from
the ancestor. So In addition to the difficulties described above IMHO converting
CPU_P5600 to a set of features activated on top of the CPU_MIPS32_R5 config
would contradict the design of the CPU-support configs implemented in the MIPS
arch subsystem.

-Sergey

> 
> Thomas.
> 
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]
Thomas Bogendoerfer May 8, 2020, 9:32 a.m. UTC | #3 
On Fri, May 08, 2020 at 12:19:23AM +0300, Serge Semin wrote:
> On Thu, May 07, 2020 at 01:17:35PM +0200, Thomas Bogendoerfer wrote:
> > P5600 is CPU_MIPS_R5 so can't you select it here and drop all the || CPU_5600
> > above/below ?
> 
> Alas, We can't do this so easy. CONFIG_CPU_MIPS32_{R2,R5,R6} and any other
> CONFIG_CPU_* configs is something that kernel config-file is supposed to select.
> Their availability is enabled by the CONFIG_SYS_HAS_CPU_* configs. CONFIG_CPU_*
> is supposed to activate CPU-specific features and there is only one
> CONFIG_CPU_x can be enabled at a time seeing it's a part of the "CPU type"
> choice kconfig menu. In addition the CPU config also tunes a compiler to activate
> the arch-specific ISA and optimizations in the arch/mips/Makefile by setting
> -march=cpu-name (where cpu-name can be p5600, mips32r5, etc).
> 
> Yes, P5600 is based on the MIPS32r5, but it also has got some specific features
> (see config CPU_P5600 and config MIPS32_R5), which makes it to be different from
> the ancestor. So In addition to the difficulties described above IMHO converting
> CPU_P5600 to a set of features activated on top of the CPU_MIPS32_R5 config
> would contradict the design of the CPU-support configs implemented in the MIPS
> arch subsystem.

maybe I wasn't clear enough, my suggestion is

use 

config CPU_P5600
	bool "MIPS Warrior P5600"
	depends on SYS_HAS_CPU_P5600
	select CPU_MIPS32_R5
	select CPU_SUPPORTS_UNCACHED_ACCELERATED
	select CPU_SUPPORTS_CPUFREQ
	select CPU_MIPSR2_IRQ_VI
	select CPU_MIPSR2_IRQ_EI

That way you don't need to any "|| CPU_P5600" where CPU_MIPS32_R5 is
already there. Or are there cases, where this would be wrong ?

Thomas.
Thomas Bogendoerfer May 8, 2020, 12:21 p.m. UTC | #4 
On Fri, May 08, 2020 at 11:32:59AM +0200, Thomas Bogendoerfer wrote:
> On Fri, May 08, 2020 at 12:19:23AM +0300, Serge Semin wrote:
> > On Thu, May 07, 2020 at 01:17:35PM +0200, Thomas Bogendoerfer wrote:
> > > P5600 is CPU_MIPS_R5 so can't you select it here and drop all the || CPU_5600
> > > above/below ?
> > 
> > Alas, We can't do this so easy. CONFIG_CPU_MIPS32_{R2,R5,R6} and any other
> > CONFIG_CPU_* configs is something that kernel config-file is supposed to select.
> > Their availability is enabled by the CONFIG_SYS_HAS_CPU_* configs. CONFIG_CPU_*
> > is supposed to activate CPU-specific features and there is only one
> > CONFIG_CPU_x can be enabled at a time seeing it's a part of the "CPU type"
> > choice kconfig menu. In addition the CPU config also tunes a compiler to activate
> > the arch-specific ISA and optimizations in the arch/mips/Makefile by setting
> > -march=cpu-name (where cpu-name can be p5600, mips32r5, etc).
> > 
> > Yes, P5600 is based on the MIPS32r5, but it also has got some specific features
> > (see config CPU_P5600 and config MIPS32_R5), which makes it to be different from
> > the ancestor. So In addition to the difficulties described above IMHO converting
> > CPU_P5600 to a set of features activated on top of the CPU_MIPS32_R5 config
> > would contradict the design of the CPU-support configs implemented in the MIPS
> > arch subsystem.
> 
> maybe I wasn't clear enough, my suggestion is
> 
> use 
> 
> config CPU_P5600
> 	bool "MIPS Warrior P5600"
> 	depends on SYS_HAS_CPU_P5600
> 	select CPU_MIPS32_R5
> 	select CPU_SUPPORTS_UNCACHED_ACCELERATED
> 	select CPU_SUPPORTS_CPUFREQ
> 	select CPU_MIPSR2_IRQ_VI
> 	select CPU_MIPSR2_IRQ_EI
> 
> That way you don't need to any "|| CPU_P5600" where CPU_MIPS32_R5 is
> already there. Or are there cases, where this would be wrong ?

nevermind, this would also need a select SYS_HAS_CPU_MIPS32_R5, which
isn't wanted here. So patch is fine as is.

Thomas.
Serge Semin May 10, 2020, 10:09 p.m. UTC | #5 
On Fri, May 08, 2020 at 02:21:37PM +0200, Thomas Bogendoerfer wrote:
> On Fri, May 08, 2020 at 11:32:59AM +0200, Thomas Bogendoerfer wrote:
> > On Fri, May 08, 2020 at 12:19:23AM +0300, Serge Semin wrote:
> > > On Thu, May 07, 2020 at 01:17:35PM +0200, Thomas Bogendoerfer wrote:
> > > > P5600 is CPU_MIPS_R5 so can't you select it here and drop all the || CPU_5600
> > > > above/below ?
> > > 
> > > Alas, We can't do this so easy. CONFIG_CPU_MIPS32_{R2,R5,R6} and any other
> > > CONFIG_CPU_* configs is something that kernel config-file is supposed to select.
> > > Their availability is enabled by the CONFIG_SYS_HAS_CPU_* configs. CONFIG_CPU_*
> > > is supposed to activate CPU-specific features and there is only one
> > > CONFIG_CPU_x can be enabled at a time seeing it's a part of the "CPU type"
> > > choice kconfig menu. In addition the CPU config also tunes a compiler to activate
> > > the arch-specific ISA and optimizations in the arch/mips/Makefile by setting
> > > -march=cpu-name (where cpu-name can be p5600, mips32r5, etc).
> > > 
> > > Yes, P5600 is based on the MIPS32r5, but it also has got some specific features
> > > (see config CPU_P5600 and config MIPS32_R5), which makes it to be different from
> > > the ancestor. So In addition to the difficulties described above IMHO converting
> > > CPU_P5600 to a set of features activated on top of the CPU_MIPS32_R5 config
> > > would contradict the design of the CPU-support configs implemented in the MIPS
> > > arch subsystem.
> > 
> > maybe I wasn't clear enough, my suggestion is
> > 
> > use 
> > 
> > config CPU_P5600
> > 	bool "MIPS Warrior P5600"
> > 	depends on SYS_HAS_CPU_P5600
> > 	select CPU_MIPS32_R5
> > 	select CPU_SUPPORTS_UNCACHED_ACCELERATED
> > 	select CPU_SUPPORTS_CPUFREQ
> > 	select CPU_MIPSR2_IRQ_VI
> > 	select CPU_MIPSR2_IRQ_EI
> > 
> > That way you don't need to any "|| CPU_P5600" where CPU_MIPS32_R5 is
> > already there. Or are there cases, where this would be wrong ?
> 
> nevermind, this would also need a select SYS_HAS_CPU_MIPS32_R5, which
> isn't wanted here. So patch is fine as is.

Ok. Thanks.

-Sergey

> 
> Thomas.
> 
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]
diff mbox series

Patch

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 55c3dbfea336..e3b780a389a9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1665,6 +1665,28 @@  config CPU_MIPS64_R6
 	  family, are based on a MIPS64r6 processor. If you own an older
 	  processor, you probably need to select MIPS64r1 or MIPS64r2 instead.
 
+config CPU_P5600
+	bool "MIPS Warrior P5600"
+	depends on SYS_HAS_CPU_P5600
+	select CPU_HAS_PREFETCH
+	select CPU_SUPPORTS_32BIT_KERNEL
+	select CPU_SUPPORTS_HIGHMEM
+	select CPU_SUPPORTS_MSA
+	select CPU_SUPPORTS_UNCACHED_ACCELERATED
+	select CPU_SUPPORTS_CPUFREQ
+	select CPU_MIPSR2_IRQ_VI
+	select CPU_MIPSR2_IRQ_EI
+	select HAVE_KVM
+	select MIPS_O32_FP64_SUPPORT
+	help
+	  Choose this option to build a kernel for MIPS Warrior P5600 CPU.
+	  It's based on MIPS32r5 ISA with XPA, EVA, dual/quad issue exec pipes,
+	  MMU with two-levels TLB, UCA, MSA, MDU core level features and system
+	  level features like up to six P5600 calculation cores, CM2 with L2
+	  cache, IOCU/IOMMU (though might be unused depending on the system-
+	  specific IP core configuration), GIC, CPC, virtualisation module,
+	  eJTAG and PDtrace.
+
 config CPU_R3000
 	bool "R3000"
 	depends on SYS_HAS_CPU_R3000
@@ -1841,7 +1863,8 @@  endchoice
 config CPU_MIPS32_3_5_FEATURES
 	bool "MIPS32 Release 3.5 Features"
 	depends on SYS_HAS_CPU_MIPS32_R3_5
-	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6
+	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_MIPS32_R6 || \
+		   CPU_P5600
 	help
 	  Choose this option to build a kernel for release 2 or later of the
 	  MIPS32 architecture including features from the 3.5 release such as
@@ -1861,7 +1884,7 @@  config CPU_MIPS32_3_5_EVA
 config CPU_MIPS32_R5_FEATURES
 	bool "MIPS32 Release 5 Features"
 	depends on SYS_HAS_CPU_MIPS32_R5
-	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5
+	depends on CPU_MIPS32_R2 || CPU_MIPS32_R5 || CPU_P5600
 	help
 	  Choose this option to build a kernel for release 2 or later of the
 	  MIPS32 architecture including features from release 5 such as
@@ -2016,6 +2039,10 @@  config SYS_HAS_CPU_MIPS64_R6
 	bool
 	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
 
+config SYS_HAS_CPU_P5600
+	bool
+	select ARCH_HAS_SYNC_DMA_FOR_CPU if DMA_NONCOHERENT
+
 config SYS_HAS_CPU_R3000
 	bool
 
@@ -2100,7 +2127,7 @@  endmenu
 config CPU_MIPS32
 	bool
 	default y if CPU_MIPS32_R1 || CPU_MIPS32_R2 || CPU_MIPS32_R5 || \
-		     CPU_MIPS32_R6
+		     CPU_MIPS32_R6 || CPU_P5600
 
 config CPU_MIPS64
 	bool
@@ -2122,7 +2149,7 @@  config CPU_MIPSR2
 
 config CPU_MIPSR5
 	bool
-	default y if CPU_MIPS32_R5
+	default y if CPU_MIPS32_R5 || CPU_P5600
 	select CPU_HAS_RIXI
 	select CPU_HAS_DIEI if !CPU_DIEI_BROKEN
 	select MIPS_SPRAM
@@ -2733,7 +2760,8 @@  config RELOCATABLE
 	bool "Relocatable kernel"
 	depends on SYS_SUPPORTS_RELOCATABLE
 	depends on CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_MIPS32_R5 || \
-		   CPU_MIPS32_R6 || CPU_MIPS64_R6 || CAVIUM_OCTEON_SOC
+		   CPU_MIPS32_R6 || CPU_MIPS64_R6 || CPU_P5600 || \
+		   CAVIUM_OCTEON_SOC
 	help
 	  This builds a kernel image that retains relocation information
 	  so it can be loaded someplace besides the default 1MB.
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 9172fb0f630b..264dead560f4 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -176,6 +176,7 @@  cflags-$(CONFIG_CPU_MIPS32_R6)	+= -march=mips32r6 -Wa,--trap -modd-spreg
 cflags-$(CONFIG_CPU_MIPS64_R1)	+= -march=mips64 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS64_R2)	+= -march=mips64r2 -Wa,--trap
 cflags-$(CONFIG_CPU_MIPS64_R6)	+= -march=mips64r6 -Wa,--trap
+cflags-$(CONFIG_CPU_P5600)	+= -march=p5600 -Wa,--trap -modd-spreg
 cflags-$(CONFIG_CPU_R5000)	+= -march=r5000 -Wa,--trap
 cflags-$(CONFIG_CPU_R5500)	+= $(call cc-option,-march=r5500,-march=r5000) \
 			-Wa,--trap
diff --git a/arch/mips/include/asm/vermagic.h b/arch/mips/include/asm/vermagic.h
index 5a0e739f597a..d03f97350f91 100644
--- a/arch/mips/include/asm/vermagic.h
+++ b/arch/mips/include/asm/vermagic.h
@@ -48,6 +48,8 @@ 
 #define MODULE_PROC_FAMILY "LOONGSON64 "
 #elif defined CONFIG_CPU_CAVIUM_OCTEON
 #define MODULE_PROC_FAMILY "OCTEON "
+#elif defined CONFIG_CPU_P5600
+#define MODULE_PROC_FAMILY "P5600 "
 #elif defined CONFIG_CPU_XLR
 #define MODULE_PROC_FAMILY "XLR "
 #elif defined CONFIG_CPU_XLP