| Message ID | 20200430220619.3169-5-ansuelsmth@gmail.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Multiple fixes in PCIe qcom driver | expand |
On Fri, 1 May 2020 00:06:11 +0200, Ansuel Smith wrote: > Add missing ext reset used by ipq8064 SoC in PCIe qcom driver. > > Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver > Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> > Cc: stable@vger.kernel.org # v4.5+ > --- > drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
Hi Ansuel, On Fri, May 01, 2020 at 12:06:11AM +0200, Ansuel Smith wrote: > Add missing ext reset used by ipq8064 SoC in PCIe qcom driver. > > Fixes: 82a823833f4e PCI: qcom: Add Qualcomm PCIe controller driver > Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> > Cc: stable@vger.kernel.org # v4.5+ > --- > drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 7a8901efc031..921030a64bab 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c [...] > @@ -347,6 +353,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) > goto err_deassert_ahb; > } > > + ret = reset_control_deassert(res->ext_reset); > + if (ret) { > + dev_err(dev, "cannot assert ext reset\n"); ^ This probably should say "cannot deassert ext reset". Apart from this, Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> regards Philipp
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 7a8901efc031..921030a64bab 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 { struct reset_control *ahb_reset; struct reset_control *por_reset; struct reset_control *phy_reset; + struct reset_control *ext_reset; struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; }; @@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) if (IS_ERR(res->por_reset)) return PTR_ERR(res->por_reset); + res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext"); + if (IS_ERR(res->ext_reset)) + return PTR_ERR(res->ext_reset); + res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); return PTR_ERR_OR_ZERO(res->phy_reset); } @@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) reset_control_assert(res->axi_reset); reset_control_assert(res->ahb_reset); reset_control_assert(res->por_reset); + reset_control_assert(res->ext_reset); reset_control_assert(res->phy_reset); clk_disable_unprepare(res->iface_clk); clk_disable_unprepare(res->core_clk); @@ -347,6 +353,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) goto err_deassert_ahb; } + ret = reset_control_deassert(res->ext_reset); + if (ret) { + dev_err(dev, "cannot assert ext reset\n"); + goto err_deassert_ahb; + } + /* enable PCIe clocks and resets */ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); val &= ~BIT(0);