| Message ID | 20200504093703.261135-1-joel@jms.id.au (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | aspeed: Support AST2600A1 silicon revision | expand |
On Mon, 4 May 2020, at 19:07, Joel Stanley wrote: > There are minimal differences from Qemu's point of view between the A0 > and A1 silicon revisions. > > As the A1 exercises different code paths in u-boot it is desirable to > emulate that instead. > > Signed-off-by: Joel Stanley <joel@jms.id.au> > --- > hw/arm/aspeed.c | 8 ++++---- > hw/arm/aspeed_ast2600.c | 6 +++--- > hw/misc/aspeed_scu.c | 11 +++++------ > include/hw/misc/aspeed_scu.h | 1 + > 4 files changed, 13 insertions(+), 13 deletions(-) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 99a0f3fcf36e..91301efab32d 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -93,7 +93,7 @@ struct AspeedBoardState { > > /* Tacoma hardware value */ > #define TACOMA_BMC_HW_STRAP1 0x00000000 > -#define TACOMA_BMC_HW_STRAP2 0x00000000 > +#define TACOMA_BMC_HW_STRAP2 0x00000040 > > /* > * The max ram region is for firmwares that scan the address space > @@ -585,7 +585,7 @@ static void > aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) > AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); > > mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; > - amc->soc_name = "ast2600-a0"; > + amc->soc_name = "ast2600-a1"; > amc->hw_strap1 = AST2600_EVB_HW_STRAP1; > amc->hw_strap2 = AST2600_EVB_HW_STRAP2; > amc->fmc_model = "w25q512jv"; > @@ -600,8 +600,8 @@ static void > aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) > MachineClass *mc = MACHINE_CLASS(oc); > AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); > > - mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; > - amc->soc_name = "ast2600-a0"; > + mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; Lol, whoops. Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
On 5/4/20 11:37 AM, Joel Stanley wrote: > There are minimal differences from Qemu's point of view between the A0 > and A1 silicon revisions. > > As the A1 exercises different code paths in u-boot it is desirable to > emulate that instead. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > hw/arm/aspeed.c | 8 ++++---- > hw/arm/aspeed_ast2600.c | 6 +++--- > hw/misc/aspeed_scu.c | 11 +++++------ > include/hw/misc/aspeed_scu.h | 1 + > 4 files changed, 13 insertions(+), 13 deletions(-) > > diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c > index 99a0f3fcf36e..91301efab32d 100644 > --- a/hw/arm/aspeed.c > +++ b/hw/arm/aspeed.c > @@ -93,7 +93,7 @@ struct AspeedBoardState { > > /* Tacoma hardware value */ > #define TACOMA_BMC_HW_STRAP1 0x00000000 > -#define TACOMA_BMC_HW_STRAP2 0x00000000 > +#define TACOMA_BMC_HW_STRAP2 0x00000040 > > /* > * The max ram region is for firmwares that scan the address space > @@ -585,7 +585,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) > AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); > > mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; > - amc->soc_name = "ast2600-a0"; > + amc->soc_name = "ast2600-a1"; > amc->hw_strap1 = AST2600_EVB_HW_STRAP1; > amc->hw_strap2 = AST2600_EVB_HW_STRAP2; > amc->fmc_model = "w25q512jv"; > @@ -600,8 +600,8 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) > MachineClass *mc = MACHINE_CLASS(oc); > AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); > > - mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; > - amc->soc_name = "ast2600-a0"; > + mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; > + amc->soc_name = "ast2600-a1"; > amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; > amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; > amc->fmc_model = "mx66l1g45g"; > diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c > index 1a869e09b96a..c6e0ab84ac86 100644 > --- a/hw/arm/aspeed_ast2600.c > +++ b/hw/arm/aspeed_ast2600.c > @@ -557,9 +557,9 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) > > dc->realize = aspeed_soc_ast2600_realize; > > - sc->name = "ast2600-a0"; > + sc->name = "ast2600-a1"; > sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); > - sc->silicon_rev = AST2600_A0_SILICON_REV; > + sc->silicon_rev = AST2600_A1_SILICON_REV; > sc->sram_size = 0x10000; > sc->spis_num = 2; > sc->ehcis_num = 2; > @@ -571,7 +571,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) > } > > static const TypeInfo aspeed_soc_ast2600_type_info = { > - .name = "ast2600-a0", > + .name = "ast2600-a1", > .parent = TYPE_ASPEED_SOC, > .instance_size = sizeof(AspeedSoCState), > .instance_init = aspeed_soc_ast2600_init, > diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c > index 9d7482a9df19..ec4fef900e27 100644 > --- a/hw/misc/aspeed_scu.c > +++ b/hw/misc/aspeed_scu.c > @@ -431,6 +431,7 @@ static uint32_t aspeed_silicon_revs[] = { > AST2500_A0_SILICON_REV, > AST2500_A1_SILICON_REV, > AST2600_A0_SILICON_REV, > + AST2600_A1_SILICON_REV, > }; > > bool is_supported_silicon_rev(uint32_t silicon_rev) > @@ -649,12 +650,10 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = { > .valid.unaligned = false, > }; > > -static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = { > - [AST2600_SILICON_REV] = AST2600_SILICON_REV, > - [AST2600_SILICON_REV2] = AST2600_SILICON_REV, > - [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100, > +static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = { > + [AST2600_SYS_RST_CTRL] = 0xF7C3FED8, > [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, > - [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B, > + [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, > [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, > [AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */ > [AST2600_HPLL_PARAM] = 0x1000405F, > @@ -684,7 +683,7 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) > > dc->desc = "ASPEED 2600 System Control Unit"; > dc->reset = aspeed_ast2600_scu_reset; > - asc->resets = ast2600_a0_resets; > + asc->resets = ast2600_a1_resets; > asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */ > asc->apb_divider = 4; > asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS; > diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h > index 1d7f7ffc1598..a6739bb846b6 100644 > --- a/include/hw/misc/aspeed_scu.h > +++ b/include/hw/misc/aspeed_scu.h > @@ -41,6 +41,7 @@ typedef struct AspeedSCUState { > #define AST2500_A0_SILICON_REV 0x04000303U > #define AST2500_A1_SILICON_REV 0x04010303U > #define AST2600_A0_SILICON_REV 0x05000303U > +#define AST2600_A1_SILICON_REV 0x05010303U > > #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) > >
On Mon, 4 May 2020 at 10:37, Joel Stanley <joel@jms.id.au> wrote: > > There are minimal differences from Qemu's point of view between the A0 > and A1 silicon revisions. > > As the A1 exercises different code paths in u-boot it is desirable to > emulate that instead. > > Signed-off-by: Joel Stanley <joel@jms.id.au> Applied to target-arm.next, thanks. -- PMM
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 99a0f3fcf36e..91301efab32d 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -93,7 +93,7 @@ struct AspeedBoardState { /* Tacoma hardware value */ #define TACOMA_BMC_HW_STRAP1 0x00000000 -#define TACOMA_BMC_HW_STRAP2 0x00000000 +#define TACOMA_BMC_HW_STRAP2 0x00000040 /* * The max ram region is for firmwares that scan the address space @@ -585,7 +585,7 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; - amc->soc_name = "ast2600-a0"; + amc->soc_name = "ast2600-a1"; amc->hw_strap1 = AST2600_EVB_HW_STRAP1; amc->hw_strap2 = AST2600_EVB_HW_STRAP2; amc->fmc_model = "w25q512jv"; @@ -600,8 +600,8 @@ static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) MachineClass *mc = MACHINE_CLASS(oc); AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); - mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; - amc->soc_name = "ast2600-a0"; + mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; + amc->soc_name = "ast2600-a1"; amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; amc->fmc_model = "mx66l1g45g"; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 1a869e09b96a..c6e0ab84ac86 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -557,9 +557,9 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) dc->realize = aspeed_soc_ast2600_realize; - sc->name = "ast2600-a0"; + sc->name = "ast2600-a1"; sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-a7"); - sc->silicon_rev = AST2600_A0_SILICON_REV; + sc->silicon_rev = AST2600_A1_SILICON_REV; sc->sram_size = 0x10000; sc->spis_num = 2; sc->ehcis_num = 2; @@ -571,7 +571,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) } static const TypeInfo aspeed_soc_ast2600_type_info = { - .name = "ast2600-a0", + .name = "ast2600-a1", .parent = TYPE_ASPEED_SOC, .instance_size = sizeof(AspeedSoCState), .instance_init = aspeed_soc_ast2600_init, diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 9d7482a9df19..ec4fef900e27 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -431,6 +431,7 @@ static uint32_t aspeed_silicon_revs[] = { AST2500_A0_SILICON_REV, AST2500_A1_SILICON_REV, AST2600_A0_SILICON_REV, + AST2600_A1_SILICON_REV, }; bool is_supported_silicon_rev(uint32_t silicon_rev) @@ -649,12 +650,10 @@ static const MemoryRegionOps aspeed_ast2600_scu_ops = { .valid.unaligned = false, }; -static const uint32_t ast2600_a0_resets[ASPEED_AST2600_SCU_NR_REGS] = { - [AST2600_SILICON_REV] = AST2600_SILICON_REV, - [AST2600_SILICON_REV2] = AST2600_SILICON_REV, - [AST2600_SYS_RST_CTRL] = 0xF7CFFEDC | 0x100, +static const uint32_t ast2600_a1_resets[ASPEED_AST2600_SCU_NR_REGS] = { + [AST2600_SYS_RST_CTRL] = 0xF7C3FED8, [AST2600_SYS_RST_CTRL2] = 0xFFFFFFFC, - [AST2600_CLK_STOP_CTRL] = 0xEFF43E8B, + [AST2600_CLK_STOP_CTRL] = 0xFFFF7F8A, [AST2600_CLK_STOP_CTRL2] = 0xFFF0FFF0, [AST2600_SDRAM_HANDSHAKE] = 0x00000040, /* SoC completed DRAM init */ [AST2600_HPLL_PARAM] = 0x1000405F, @@ -684,7 +683,7 @@ static void aspeed_2600_scu_class_init(ObjectClass *klass, void *data) dc->desc = "ASPEED 2600 System Control Unit"; dc->reset = aspeed_ast2600_scu_reset; - asc->resets = ast2600_a0_resets; + asc->resets = ast2600_a1_resets; asc->calc_hpll = aspeed_2500_scu_calc_hpll; /* No change since AST2500 */ asc->apb_divider = 4; asc->nr_regs = ASPEED_AST2600_SCU_NR_REGS; diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 1d7f7ffc1598..a6739bb846b6 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -41,6 +41,7 @@ typedef struct AspeedSCUState { #define AST2500_A0_SILICON_REV 0x04000303U #define AST2500_A1_SILICON_REV 0x04010303U #define AST2600_A0_SILICON_REV 0x05000303U +#define AST2600_A1_SILICON_REV 0x05010303U #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
There are minimal differences from Qemu's point of view between the A0 and A1 silicon revisions. As the A1 exercises different code paths in u-boot it is desirable to emulate that instead. Signed-off-by: Joel Stanley <joel@jms.id.au> --- hw/arm/aspeed.c | 8 ++++---- hw/arm/aspeed_ast2600.c | 6 +++--- hw/misc/aspeed_scu.c | 11 +++++------ include/hw/misc/aspeed_scu.h | 1 + 4 files changed, 13 insertions(+), 13 deletions(-)