[v3,0/4] PCI: brcmstb: Some minor fixes/features

Message

Jim Quinlan May 7, 2020, 8:15 p.m. UTC

v3 -- A change was submitted to [1] to make 'aspm-no-l0s' a general
      property for PCIe devices.  As such, the STB PCIe YAML  file
      merely notes that it may be used.

v2 -- Dropped commit concerning CRS.
   -- Chanded new prop 'brcm,aspm-en-l0s' to 'aspm-no-l0s'.
   -- Capitalize first letter in commit subject line; spelling.

v1 -- original

[1] https://github.com/devicetree-org/dt-schema/blob/master/schemas/pci/pci-bus.yaml

Jim Quinlan (4):
  PCI: brcmstb: Don't clk_put() a managed clock
  PCI: brcmstb: Fix window register offset from 4 to 8
  dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
  PCI: brcmstb: Disable L0s component of ASPM if requested

 .../bindings/pci/brcm,stb-pcie.yaml           |  2 ++
 drivers/pci/controller/pcie-brcmstb.c         | 19 +++++++++++++++----
 2 files changed, 17 insertions(+), 4 deletions(-)

Comments

Lorenzo Pieralisi May 11, 2020, 10:52 a.m. UTC | #1

On Thu, May 07, 2020 at 04:15:39PM -0400, Jim Quinlan wrote:
> v3 -- A change was submitted to [1] to make 'aspm-no-l0s' a general
>       property for PCIe devices.  As such, the STB PCIe YAML  file
>       merely notes that it may be used.
> 
> v2 -- Dropped commit concerning CRS.
>    -- Chanded new prop 'brcm,aspm-en-l0s' to 'aspm-no-l0s'.
>    -- Capitalize first letter in commit subject line; spelling.
> 
> v1 -- original
> 
> [1] https://github.com/devicetree-org/dt-schema/blob/master/schemas/pci/pci-bus.yaml
> 
> Jim Quinlan (4):
>   PCI: brcmstb: Don't clk_put() a managed clock
>   PCI: brcmstb: Fix window register offset from 4 to 8
>   dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
>   PCI: brcmstb: Disable L0s component of ASPM if requested
> 
>  .../bindings/pci/brcm,stb-pcie.yaml           |  2 ++
>  drivers/pci/controller/pcie-brcmstb.c         | 19 +++++++++++++++----
>  2 files changed, 17 insertions(+), 4 deletions(-)

Applied to pci/brcmstb, thanks !

Lorenzo