diff mbox series

[3/5] dt-bindings: ufs: ti: Fix address properties handling

Message ID 20200512204543.22090-3-robh@kernel.org (mailing list archive)
State Mainlined
Commit 346dda3167ff4f15321547114e4c9d4b132fa368
Headers show
Series [1/5] spi: dt-bindings: sifive: Add missing 2nd register region | expand

Commit Message

Rob Herring (Arm) May 12, 2020, 8:45 p.m. UTC
The ti,j721e-ufs schema and example have a couple of problems related to
address properties. First, the default #size-cells and #address-cells
are 1 for examples, so they need to be overriden with a bus node.
Second, address translation for the child ufs node is broken because
'ranges', '#address-cells', and '#size-cells' are missing from the
schema.

Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
Please ack, dependency for patch 5.

 .../devicetree/bindings/ufs/ti,j721e-ufs.yaml | 57 ++++++++++++-------
 1 file changed, 36 insertions(+), 21 deletions(-)

Comments

Vignesh Raghavendra May 13, 2020, 7:49 a.m. UTC | #1
On 13/05/20 2:15 am, Rob Herring wrote:
> The ti,j721e-ufs schema and example have a couple of problems related to
> address properties. First, the default #size-cells and #address-cells
> are 1 for examples, so they need to be overriden with a bus node.
> Second, address translation for the child ufs node is broken because
> 'ranges', '#address-cells', and '#size-cells' are missing from the
> schema.
> 
> Cc: Vignesh Raghavendra <vigneshr@ti.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---

Acked-by: Vignesh Raghavendra <vigneshr@ti.com>

Regards
Vignesh

> Please ack, dependency for patch 5.
> 
>  .../devicetree/bindings/ufs/ti,j721e-ufs.yaml | 57 ++++++++++++-------
>  1 file changed, 36 insertions(+), 21 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
> index c8a2a92074df..b503b1a918a5 100644
> --- a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
> @@ -25,6 +25,14 @@ properties:
>    power-domains:
>      maxItems: 1
>  
> +  "#address-cells":
> +    const: 2
> +
> +  "#size-cells":
> +    const: 2
> +
> +  ranges: true
> +
>  required:
>    - compatible
>    - reg
> @@ -44,25 +52,32 @@ examples:
>      #include <dt-bindings/interrupt-controller/irq.h>
>      #include <dt-bindings/interrupt-controller/arm-gic.h>
>  
> -    ufs_wrapper: ufs-wrapper@4e80000 {
> -       compatible = "ti,j721e-ufs";
> -       reg = <0x0 0x4e80000 0x0 0x100>;
> -       power-domains = <&k3_pds 277>;
> -       clocks = <&k3_clks 277 1>;
> -       assigned-clocks = <&k3_clks 277 1>;
> -       assigned-clock-parents = <&k3_clks 277 4>;
> -       #address-cells = <2>;
> -       #size-cells = <2>;
> -
> -       ufs@4e84000 {
> -          compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
> -          reg = <0x0 0x4e84000 0x0 0x10000>;
> -          interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> -          freq-table-hz = <19200000 19200000>;
> -          power-domains = <&k3_pds 277>;
> -          clocks = <&k3_clks 277 1>;
> -          assigned-clocks = <&k3_clks 277 1>;
> -          assigned-clock-parents = <&k3_clks 277 4>;
> -          clock-names = "core_clk";
> -       };
> +    bus {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        ufs-wrapper@4e80000 {
> +            compatible = "ti,j721e-ufs";
> +            reg = <0x0 0x4e80000 0x0 0x100>;
> +            power-domains = <&k3_pds 277>;
> +            clocks = <&k3_clks 277 1>;
> +            assigned-clocks = <&k3_clks 277 1>;
> +            assigned-clock-parents = <&k3_clks 277 4>;
> +
> +            ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
> +            #address-cells = <2>;
> +            #size-cells = <2>;
> +
> +            ufs@4000 {
> +                compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
> +                reg = <0x0 0x4000 0x0 0x10000>;
> +                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +                freq-table-hz = <19200000 19200000>;
> +                power-domains = <&k3_pds 277>;
> +                clocks = <&k3_clks 277 1>;
> +                assigned-clocks = <&k3_clks 277 1>;
> +                assigned-clock-parents = <&k3_clks 277 4>;
> +                clock-names = "core_clk";
> +            };
> +        };
>      };
>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
index c8a2a92074df..b503b1a918a5 100644
--- a/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/ti,j721e-ufs.yaml
@@ -25,6 +25,14 @@  properties:
   power-domains:
     maxItems: 1
 
+  "#address-cells":
+    const: 2
+
+  "#size-cells":
+    const: 2
+
+  ranges: true
+
 required:
   - compatible
   - reg
@@ -44,25 +52,32 @@  examples:
     #include <dt-bindings/interrupt-controller/irq.h>
     #include <dt-bindings/interrupt-controller/arm-gic.h>
 
-    ufs_wrapper: ufs-wrapper@4e80000 {
-       compatible = "ti,j721e-ufs";
-       reg = <0x0 0x4e80000 0x0 0x100>;
-       power-domains = <&k3_pds 277>;
-       clocks = <&k3_clks 277 1>;
-       assigned-clocks = <&k3_clks 277 1>;
-       assigned-clock-parents = <&k3_clks 277 4>;
-       #address-cells = <2>;
-       #size-cells = <2>;
-
-       ufs@4e84000 {
-          compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
-          reg = <0x0 0x4e84000 0x0 0x10000>;
-          interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
-          freq-table-hz = <19200000 19200000>;
-          power-domains = <&k3_pds 277>;
-          clocks = <&k3_clks 277 1>;
-          assigned-clocks = <&k3_clks 277 1>;
-          assigned-clock-parents = <&k3_clks 277 4>;
-          clock-names = "core_clk";
-       };
+    bus {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        ufs-wrapper@4e80000 {
+            compatible = "ti,j721e-ufs";
+            reg = <0x0 0x4e80000 0x0 0x100>;
+            power-domains = <&k3_pds 277>;
+            clocks = <&k3_clks 277 1>;
+            assigned-clocks = <&k3_clks 277 1>;
+            assigned-clock-parents = <&k3_clks 277 4>;
+
+            ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
+            #address-cells = <2>;
+            #size-cells = <2>;
+
+            ufs@4000 {
+                compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
+                reg = <0x0 0x4000 0x0 0x10000>;
+                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                freq-table-hz = <19200000 19200000>;
+                power-domains = <&k3_pds 277>;
+                clocks = <&k3_clks 277 1>;
+                assigned-clocks = <&k3_clks 277 1>;
+                assigned-clock-parents = <&k3_clks 277 4>;
+                clock-names = "core_clk";
+            };
+        };
     };