diff mbox series

[5/6] drm/i915: Extract i915_cs_timestamp_{ns_to_ticks, tick_to_ns}()

Message ID 20200302143943.32676-5-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show
Series [1/6] drm/i915: Nuke pointless div by 64bit | expand

Commit Message

Ville Syrjälä March 2, 2020, 2:39 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Pull the code to do the CS timestamp ns<->ticks conversion into
helpers and use them all over.

The check in i915_perf_noa_delay_set() seems a bit dubious,
so we switch it to do what I assume it wanted to do all along
(ie. make sure the resulting delay in CS timestamp ticks
doesn't exceed 32bits)?

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c        |  3 +--
 drivers/gpu/drm/i915/i915_drv.h            | 12 ++++++++++++
 drivers/gpu/drm/i915/i915_perf.c           |  7 ++-----
 drivers/gpu/drm/i915/intel_device_info.c   |  2 +-
 drivers/gpu/drm/i915/selftests/i915_perf.c |  3 +--
 5 files changed, 17 insertions(+), 10 deletions(-)

Comments

Chris Wilson May 13, 2020, 3:09 p.m. UTC | #1 
Quoting Ville Syrjala (2020-03-02 14:39:42)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Pull the code to do the CS timestamp ns<->ticks conversion into
> helpers and use them all over.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
 
> The check in i915_perf_noa_delay_set() seems a bit dubious,
> so we switch it to do what I assume it wanted to do all along
> (ie. make sure the resulting delay in CS timestamp ticks
> doesn't exceed 32bits)?

Yes. The MI_MATH operates on just 32b of the timestamp, and so wants a
delay in that range.
-Chris
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index c0e54c500017..4bfa70b94e8f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1890,13 +1890,12 @@  static int
 i915_perf_noa_delay_set(void *data, u64 val)
 {
 	struct drm_i915_private *i915 = data;
-	const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 1000;
 
 	/*
 	 * This would lead to infinite waits as we're doing timestamp
 	 * difference on the CS with only 32bits.
 	 */
-	if (val > mul_u32_u32(U32_MAX, clk))
+	if (i915_cs_timestamp_ns_to_ticks(i915, val) > U32_MAX)
 		return -EINVAL;
 
 	atomic64_set(&i915->perf.noa_programming_delay, val);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1f5dda38e7b4..7640eccdc46c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1955,4 +1955,16 @@  i915_coherent_map_type(struct drm_i915_private *i915)
 	return HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
 }
 
+static inline u64 i915_cs_timestamp_ns_to_ticks(struct drm_i915_private *i915, u64 val)
+{
+	return DIV_ROUND_UP_ULL(val * RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
+				1000000000);
+}
+
+static inline u64 i915_cs_timestamp_ticks_to_ns(struct drm_i915_private *i915, u64 val)
+{
+	return div_u64(val * 1000000000,
+		       RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a2f98fb08bf1..f53e2c72ae97 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1667,9 +1667,7 @@  static int alloc_noa_wait(struct i915_perf_stream *stream)
 	struct drm_i915_gem_object *bo;
 	struct i915_vma *vma;
 	const u64 delay_ticks = 0xffffffffffffffff -
-		DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
-				 RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
-				 1000000000);
+		i915_cs_timestamp_ns_to_ticks(i915, atomic64_read(&stream->perf->noa_programming_delay));
 	const u32 base = stream->engine->mmio_base;
 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
 	u32 *batch, *ts0, *cs, *jump;
@@ -3466,8 +3464,7 @@  i915_perf_open_ioctl_locked(struct i915_perf *perf,
 
 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
 {
-	return div_u64(1000000000 * (2ULL << exponent),
-		       RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_hz);
+	return i915_cs_timestamp_ticks_to_ns(perf->i915, 2ULL << exponent);
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index be88eb41035a..d97a0e09b6b2 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -1073,7 +1073,7 @@  void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		read_timestamp_frequency(dev_priv);
 	if (runtime->cs_timestamp_frequency_hz) {
 		runtime->cs_timestamp_period_ns =
-			div_u64(1e9, runtime->cs_timestamp_frequency_hz);
+			i915_cs_timestamp_ticks_to_ns(dev_priv, 1);
 		drm_dbg(&dev_priv->drm,
 			"CS timestamp wraparound in %lldms\n",
 			div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns,
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
index dea0c5dd2739..c6f3374062c5 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -180,8 +180,7 @@  static int live_noa_delay(void *arg)
 
 	delay = intel_read_status_page(stream->engine, 0x102);
 	delay -= intel_read_status_page(stream->engine, 0x100);
-	delay = div_u64(mul_u32_u32(delay, 1000000000),
-			RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
+	delay = i915_cs_timestamp_ticks_to_ns(i915, delay);
 	pr_info("GPU delay: %uns, expected %lluns\n",
 		delay, expected);