| Message ID | 1589359366-1669-15-git-send-email-chenhc@lemote.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | KVM: MIPS: Add Loongson-3 support (Host Side) | expand |
сре, 13. мај 2020. у 10:48 Huacai Chen <chenhc@lemote.com> је написао/ла: > > This patch enable KVM support for Loongson-3 by selecting HAVE_KVM, but > only enable KVM/VZ on Loongson-3A R4+ (because VZ of early processors > are incomplete). Besides, Loongson-3 support SMP guests, so we clear the > linked load bit of LLAddr in kvm_vz_vcpu_load() if the guest has more > than one VCPUs. > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- Reviewed-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> > arch/mips/Kconfig | 1 + > arch/mips/kernel/cpu-probe.c | 1 + > arch/mips/kvm/vz.c | 2 +- > 3 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index ce1aacc..3a15f2b 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1405,6 +1405,7 @@ config CPU_LOONGSON64 > select MIPS_L1_CACHE_SHIFT_6 > select GPIOLIB > select SWIOTLB > + select HAVE_KVM > help > The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor > cores implements the MIPS64R2 instruction set with many extensions, > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index 319c250..415fbd2 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -2008,6 +2008,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) > c->writecombine = _CACHE_UNCACHED_ACCELERATED; > c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | > MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); > + c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ > break; > case PRID_IMP_LOONGSON_64G: > c->cputype = CPU_LOONGSON64; > diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c > index 73701c3..dc753d0 100644 > --- a/arch/mips/kvm/vz.c > +++ b/arch/mips/kvm/vz.c > @@ -2697,7 +2697,7 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu) > * prevents a SC on the next VCPU from succeeding by matching a LL on > * the previous VCPU. > */ > - if (cpu_guest_has_rw_llb) > + if (vcpu->kvm->created_vcpus > 1) > write_gc0_lladdr(0); > > return 0; > -- > 2.7.0 >
On Wed, May 13, 2020 at 04:42:45PM +0800, Huacai Chen wrote: > This patch enable KVM support for Loongson-3 by selecting HAVE_KVM, but > only enable KVM/VZ on Loongson-3A R4+ (because VZ of early processors > are incomplete). Besides, Loongson-3 support SMP guests, so we clear the > linked load bit of LLAddr in kvm_vz_vcpu_load() if the guest has more > than one VCPUs. > > Signed-off-by: Huacai Chen <chenhc@lemote.com> > Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > arch/mips/Kconfig | 1 + > arch/mips/kernel/cpu-probe.c | 1 + > arch/mips/kvm/vz.c | 2 +- > 3 files changed, 3 insertions(+), 1 deletion(-) Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Thomas.
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ce1aacc..3a15f2b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1405,6 +1405,7 @@ config CPU_LOONGSON64 select MIPS_L1_CACHE_SHIFT_6 select GPIOLIB select SWIOTLB + select HAVE_KVM help The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor cores implements the MIPS64R2 instruction set with many extensions, diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 319c250..415fbd2 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -2008,6 +2008,7 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) c->writecombine = _CACHE_UNCACHED_ACCELERATED; c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM | MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2); + c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */ break; case PRID_IMP_LOONGSON_64G: c->cputype = CPU_LOONGSON64; diff --git a/arch/mips/kvm/vz.c b/arch/mips/kvm/vz.c index 73701c3..dc753d0 100644 --- a/arch/mips/kvm/vz.c +++ b/arch/mips/kvm/vz.c @@ -2697,7 +2697,7 @@ static int kvm_vz_vcpu_load(struct kvm_vcpu *vcpu, int cpu) * prevents a SC on the next VCPU from succeeding by matching a LL on * the previous VCPU. */ - if (cpu_guest_has_rw_llb) + if (vcpu->kvm->created_vcpus > 1) write_gc0_lladdr(0); return 0;
This patch enable KVM support for Loongson-3 by selecting HAVE_KVM, but only enable KVM/VZ on Loongson-3A R4+ (because VZ of early processors are incomplete). Besides, Loongson-3 support SMP guests, so we clear the linked load bit of LLAddr in kvm_vz_vcpu_load() if the guest has more than one VCPUs. Signed-off-by: Huacai Chen <chenhc@lemote.com> Co-developed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- arch/mips/Kconfig | 1 + arch/mips/kernel/cpu-probe.c | 1 + arch/mips/kvm/vz.c | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-)