| Message ID | 20200513071344.5430-4-frank.wang@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Rockchip RK3399 USB3.0 Host support | expand |
On 2020/5/13 下午3:13, Frank Wang wrote: > From: Jagan Teki <jagan@amarulasolutions.com> > > Enable/Disable TCPHY clock for rk3399 platform. > > Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/clk/rockchip/clk_rk3399.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c > index 98fc6a3267..06232f1903 100644 > --- a/drivers/clk/rockchip/clk_rk3399.c > +++ b/drivers/clk/rockchip/clk_rk3399.c > @@ -1144,6 +1144,18 @@ static int rk3399_clk_enable(struct clk *clk) > case HCLK_HOST1_ARB: > rk_clrreg(&priv->cru->clksel_con[20], BIT(8)); > break; > + case SCLK_UPHY0_TCPDPHY_REF: > + rk_clrreg(&priv->cru->clkgate_con[13], BIT(4)); > + break; > + case SCLK_UPHY0_TCPDCORE: > + rk_clrreg(&priv->cru->clkgate_con[13], BIT(5)); > + break; > + case SCLK_UPHY1_TCPDPHY_REF: > + rk_clrreg(&priv->cru->clkgate_con[13], BIT(6)); > + break; > + case SCLK_UPHY1_TCPDCORE: > + rk_clrreg(&priv->cru->clkgate_con[13], BIT(7)); > + break; > case SCLK_PCIEPHY_REF: > rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); > break; > @@ -1226,6 +1238,18 @@ static int rk3399_clk_disable(struct clk *clk) > case HCLK_HOST1_ARB: > rk_setreg(&priv->cru->clksel_con[20], BIT(8)); > break; > + case SCLK_UPHY0_TCPDPHY_REF: > + rk_setreg(&priv->cru->clkgate_con[13], BIT(4)); > + break; > + case SCLK_UPHY0_TCPDCORE: > + rk_setreg(&priv->cru->clkgate_con[13], BIT(5)); > + break; > + case SCLK_UPHY1_TCPDPHY_REF: > + rk_setreg(&priv->cru->clkgate_con[13], BIT(6)); > + break; > + case SCLK_UPHY1_TCPDCORE: > + rk_setreg(&priv->cru->clkgate_con[13], BIT(7)); > + break; > case SCLK_PCIEPHY_REF: > rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); > break;
diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 98fc6a3267..06232f1903 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1144,6 +1144,18 @@ static int rk3399_clk_enable(struct clk *clk) case HCLK_HOST1_ARB: rk_clrreg(&priv->cru->clksel_con[20], BIT(8)); break; + case SCLK_UPHY0_TCPDPHY_REF: + rk_clrreg(&priv->cru->clkgate_con[13], BIT(4)); + break; + case SCLK_UPHY0_TCPDCORE: + rk_clrreg(&priv->cru->clkgate_con[13], BIT(5)); + break; + case SCLK_UPHY1_TCPDPHY_REF: + rk_clrreg(&priv->cru->clkgate_con[13], BIT(6)); + break; + case SCLK_UPHY1_TCPDCORE: + rk_clrreg(&priv->cru->clkgate_con[13], BIT(7)); + break; case SCLK_PCIEPHY_REF: rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); break; @@ -1226,6 +1238,18 @@ static int rk3399_clk_disable(struct clk *clk) case HCLK_HOST1_ARB: rk_setreg(&priv->cru->clksel_con[20], BIT(8)); break; + case SCLK_UPHY0_TCPDPHY_REF: + rk_setreg(&priv->cru->clkgate_con[13], BIT(4)); + break; + case SCLK_UPHY0_TCPDCORE: + rk_setreg(&priv->cru->clkgate_con[13], BIT(5)); + break; + case SCLK_UPHY1_TCPDPHY_REF: + rk_setreg(&priv->cru->clkgate_con[13], BIT(6)); + break; + case SCLK_UPHY1_TCPDCORE: + rk_setreg(&priv->cru->clkgate_con[13], BIT(7)); + break; case SCLK_PCIEPHY_REF: rk_clrreg(&priv->cru->clksel_con[18], BIT(10)); break;