| Message ID | 3a451e360fed84bc40287678b4d6be13821cfbc0.1587760454.git.hns@goldelico.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) | expand |
Hi Nikolaus, Le ven. 24 avril 2020 à 22:34, H. Nikolaus Schaller <hns@goldelico.com> a écrit : > The Imagination PVR/SGX GPU is part of several SoC from > multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, > Allwinner A83 and others. > > With this binding, we describe how the SGX processor is > interfaced to the SoC (registers and interrupt). > > The interface also consists of clocks, reset, power but > information from data sheets is vague and some SoC integrators > (TI) deciced to use a PRCM wrapper (ti,sysc) which does > all clock, reset and power-management through registers > outside of the sgx register block. > > Therefore all these properties are optional. > > Tested by make dt_binding_check > > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> > --- > .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 > ++++++++++++++++++ > 1 file changed, 150 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > > diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > new file mode 100644 > index 000000000000..33a9c4c6e784 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Imagination PVR/SGX GPU > + > +maintainers: > + - H. Nikolaus Schaller <hns@goldelico.com> > + > +description: |+ > + This binding describes the Imagination SGX5 series of 3D > accelerators which > + are found in several different SoC like TI OMAP, Sitara, Ingenic > JZ4780, > + Allwinner A83, and Intel Poulsbo and CedarView and more. > + > + For an extensive list see: > https://en.wikipedia.org/wiki/PowerVR#Implementations > + > + The SGX node is usually a child node of some DT node belonging to > the SoC > + which handles clocks, reset and general address space mapping of > the SGX > + register area. If not, an optional clock can be specified here. > + > +properties: > + $nodename: > + pattern: '^gpu@[a-f0-9]+$' > + compatible: > + oneOf: > + - description: SGX530-121 based SoC > + items: > + - enum: > + - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora > 600MHz and similar > + - const: img,sgx530-121 > + - const: img,sgx530 > + > + - description: SGX530-125 based SoC > + items: > + - enum: > + - ti,am3352-sgx530-125 # BeagleBone Black > + - ti,am3517-sgx530-125 > + - ti,am4-sgx530-125 > + - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, > OpenPandora 1GHz and similar > + - ti,ti81xx-sgx530-125 > + - const: ti,omap3-sgx530-125 > + - const: img,sgx530-125 > + - const: img,sgx530 > + > + - description: SGX535-116 based SoC > + items: > + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx > + - const: img,sgx535-116 > + - const: img,sgx535 > + > + - description: SGX540-116 based SoC > + items: > + - const: intel,medfield-gma-sgx540 # Atom Z24xx > + - const: img,sgx540-116 > + - const: img,sgx540 > + > + - description: SGX540-120 based SoC > + items: > + - enum: > + - samsung,s5pv210-sgx540-120 > + - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and > similar > + - const: img,sgx540-120 > + - const: img,sgx540 > + > + - description: SGX540-130 based SoC > + items: > + - enum: > + - ingenic,jz4780-sgx540-130 # CI20 > + - const: img,sgx540-130 > + - const: img,sgx540 > + > + - description: SGX544-112 based SoC > + items: > + - const: ti,omap4470-sgx544-112 > + - const: img,sgx544-112 > + - const: img,sgx544 > + > + - description: SGX544-115 based SoC > + items: > + - enum: > + - allwinner,sun8i-a31-sgx544-115 > + - allwinner,sun8i-a31s-sgx544-115 > + - allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 > (Allwinner A83T) and similar > + - const: img,sgx544-115 > + - const: img,sgx544 > + > + - description: SGX544-116 based SoC > + items: > + - enum: > + - ti,dra7-sgx544-116 # DRA7 > + - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and > similar > + - const: img,sgx544-116 > + - const: img,sgx544 > + > + - description: SGX545 based SoC > + items: > + - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500 > + - const: img,sgx545-116 > + - const: img,sgx545 > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + interrupt-names: > + maxItems: 1 > + items: > + - const: sgx > + > + clocks: > + maxItems: 4 > + > + clock-names: > + maxItems: 4 > + items: > + - const: core > + - const: sys > + - const: mem > + - const: hyd > + > + sgx-supply: true > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts By not making 'clocks' required you make it possible to create broken bindings; according to your schema, a GPU node without a 'clocks' for the JZ4780 would be perfectly valid. It's possible to forbid the presence of the 'clocks' property on some implementations, and require it on others. See how it's done for instance on Documentation/devicetree/bindings/serial/samsung_uart.yaml. -Paul > + > +additionalProperties: false > + > +examples: > + - |+ > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + gpu: gpu@fe00 { > + compatible = "ti,omap5-sgx544-116", "img,sgx544-116", > "img,sgx544"; > + reg = <0xfe00 0x200>; > + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > +... > -- > 2.25.1 >
Hi Nikolaus, On 24.04.20 22:34, H. Nikolaus Schaller wrote: > The Imagination PVR/SGX GPU is part of several SoC from > multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, > Allwinner A83 and others. > > With this binding, we describe how the SGX processor is > interfaced to the SoC (registers and interrupt). > > The interface also consists of clocks, reset, power but > information from data sheets is vague and some SoC integrators > (TI) deciced to use a PRCM wrapper (ti,sysc) which does > all clock, reset and power-management through registers > outside of the sgx register block. > > Therefore all these properties are optional. > > Tested by make dt_binding_check > > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> > --- > .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++++++++++++++++++ > 1 file changed, 150 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > > diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > new file mode 100644 > index 000000000000..33a9c4c6e784 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Imagination PVR/SGX GPU > + > +maintainers: > + - H. Nikolaus Schaller <hns@goldelico.com> > + > +description: |+ > + This binding describes the Imagination SGX5 series of 3D accelerators which > + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780, > + Allwinner A83, and Intel Poulsbo and CedarView and more. > + > + For an extensive list see: https://en.wikipedia.org/wiki/PowerVR#Implementations > + > + The SGX node is usually a child node of some DT node belonging to the SoC > + which handles clocks, reset and general address space mapping of the SGX > + register area. If not, an optional clock can be specified here. > + > +properties: > + $nodename: > + pattern: '^gpu@[a-f0-9]+$' > + compatible: > + oneOf: > + - description: SGX530-121 based SoC > + items: > + - enum: > + - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar > + - const: img,sgx530-121 > + - const: img,sgx530 > + > + - description: SGX530-125 based SoC > + items: > + - enum: > + - ti,am3352-sgx530-125 # BeagleBone Black > + - ti,am3517-sgx530-125 > + - ti,am4-sgx530-125 > + - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz and similar > + - ti,ti81xx-sgx530-125 > + - const: ti,omap3-sgx530-125 > + - const: img,sgx530-125 > + - const: img,sgx530 > + > + - description: SGX535-116 based SoC > + items: > + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx > + - const: img,sgx535-116 > + - const: img,sgx535 > + > + - description: SGX540-116 based SoC > + items: > + - const: intel,medfield-gma-sgx540 # Atom Z24xx > + - const: img,sgx540-116 > + - const: img,sgx540 > + > + - description: SGX540-120 based SoC > + items: > + - enum: > + - samsung,s5pv210-sgx540-120 > + - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar > + - const: img,sgx540-120 > + - const: img,sgx540 > + > + - description: SGX540-130 based SoC > + items: > + - enum: > + - ingenic,jz4780-sgx540-130 # CI20 > + - const: img,sgx540-130 > + - const: img,sgx540 > + > + - description: SGX544-112 based SoC > + items: > + - const: ti,omap4470-sgx544-112 > + - const: img,sgx544-112 > + - const: img,sgx544 > + > + - description: SGX544-115 based SoC > + items: > + - enum: > + - allwinner,sun8i-a31-sgx544-115 > + - allwinner,sun8i-a31s-sgx544-115 those two bindings are wrong. It should be allwinner,sun6i-a31-sgx544-115 and allwinner,sun6i-a31s-sgx544-115. I did a copy paste error in the patches that I provided for this series. Cheers, Philipp
Hi Philipp, > Am 26.04.2020 um 21:36 schrieb Philipp Rossak <embed3d@gmail.com>: > > Hi Nikolaus, > > On 24.04.20 22:34, H. Nikolaus Schaller wrote: >> The Imagination PVR/SGX GPU is part of several SoC from >> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, >> Allwinner A83 and others. >> With this binding, we describe how the SGX processor is >> interfaced to the SoC (registers and interrupt). >> The interface also consists of clocks, reset, power but >> information from data sheets is vague and some SoC integrators >> (TI) deciced to use a PRCM wrapper (ti,sysc) which does >> all clock, reset and power-management through registers >> outside of the sgx register block. >> Therefore all these properties are optional. >> Tested by make dt_binding_check >> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> >> --- >> .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++++++++++++++++++ >> 1 file changed, 150 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> new file mode 100644 >> index 000000000000..33a9c4c6e784 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> @@ -0,0 +1,150 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Imagination PVR/SGX GPU >> + ... >> + - description: SGX544-112 based SoC >> + items: >> + - const: ti,omap4470-sgx544-112 >> + - const: img,sgx544-112 >> + - const: img,sgx544 >> + >> + - description: SGX544-115 based SoC >> + items: >> + - enum: >> + - allwinner,sun8i-a31-sgx544-115 >> + - allwinner,sun8i-a31s-sgx544-115 > those two bindings are wrong. > It should be allwinner,sun6i-a31-sgx544-115 and allwinner,sun6i-a31s-sgx544-115. I did a copy paste error in the patches that I provided for this series. Ok, noted for v8. BR and thanks, Nikolaus
Hi Paul, > Am 26.04.2020 um 15:11 schrieb Paul Cercueil <paul@crapouillou.net>: > > Hi Nikolaus, > > Le ven. 24 avril 2020 à 22:34, H. Nikolaus Schaller <hns@goldelico.com> a écrit : >> The Imagination PVR/SGX GPU is part of several SoC from >> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, >> Allwinner A83 and others. >> With this binding, we describe how the SGX processor is >> interfaced to the SoC (registers and interrupt). >> The interface also consists of clocks, reset, power but >> information from data sheets is vague and some SoC integrators >> (TI) deciced to use a PRCM wrapper (ti,sysc) which does >> all clock, reset and power-management through registers >> outside of the sgx register block. >> Therefore all these properties are optional. >> Tested by make dt_binding_check >> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> >> --- >> .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++++++++++++++++++ >> 1 file changed, 150 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> new file mode 100644 >> index 000000000000..33a9c4c6e784 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >> @@ -0,0 +1,150 @@ >> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Imagination PVR/SGX GPU >> + >> +maintainers: >> + - H. Nikolaus Schaller <hns@goldelico.com> >> + >> +description: |+ >> + This binding describes the Imagination SGX5 series of 3D accelerators which >> + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780, >> + Allwinner A83, and Intel Poulsbo and CedarView and more. >> + >> + For an extensive list see: https://en.wikipedia.org/wiki/PowerVR#Implementations >> + >> + The SGX node is usually a child node of some DT node belonging to the SoC >> + which handles clocks, reset and general address space mapping of the SGX >> + register area. If not, an optional clock can be specified here. >> + >> +properties: >> + $nodename: >> + pattern: '^gpu@[a-f0-9]+$' >> + compatible: >> + oneOf: >> + - description: SGX530-121 based SoC >> + items: >> + - enum: >> + - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar >> + - const: img,sgx530-121 >> + - const: img,sgx530 >> + >> + - description: SGX530-125 based SoC >> + items: >> + - enum: >> + - ti,am3352-sgx530-125 # BeagleBone Black >> + - ti,am3517-sgx530-125 >> + - ti,am4-sgx530-125 >> + - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz and similar >> + - ti,ti81xx-sgx530-125 >> + - const: ti,omap3-sgx530-125 >> + - const: img,sgx530-125 >> + - const: img,sgx530 >> + >> + - description: SGX535-116 based SoC >> + items: >> + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx >> + - const: img,sgx535-116 >> + - const: img,sgx535 >> + >> + - description: SGX540-116 based SoC >> + items: >> + - const: intel,medfield-gma-sgx540 # Atom Z24xx >> + - const: img,sgx540-116 >> + - const: img,sgx540 >> + >> + - description: SGX540-120 based SoC >> + items: >> + - enum: >> + - samsung,s5pv210-sgx540-120 >> + - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar >> + - const: img,sgx540-120 >> + - const: img,sgx540 >> + >> + - description: SGX540-130 based SoC >> + items: >> + - enum: >> + - ingenic,jz4780-sgx540-130 # CI20 >> + - const: img,sgx540-130 >> + - const: img,sgx540 >> + >> + - description: SGX544-112 based SoC >> + items: >> + - const: ti,omap4470-sgx544-112 >> + - const: img,sgx544-112 >> + - const: img,sgx544 >> + >> + - description: SGX544-115 based SoC >> + items: >> + - enum: >> + - allwinner,sun8i-a31-sgx544-115 >> + - allwinner,sun8i-a31s-sgx544-115 >> + - allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 (Allwinner A83T) and similar >> + - const: img,sgx544-115 >> + - const: img,sgx544 >> + >> + - description: SGX544-116 based SoC >> + items: >> + - enum: >> + - ti,dra7-sgx544-116 # DRA7 >> + - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar >> + - const: img,sgx544-116 >> + - const: img,sgx544 >> + >> + - description: SGX545 based SoC >> + items: >> + - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500 >> + - const: img,sgx545-116 >> + - const: img,sgx545 >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + interrupt-names: >> + maxItems: 1 >> + items: >> + - const: sgx >> + >> + clocks: >> + maxItems: 4 >> + >> + clock-names: >> + maxItems: 4 >> + items: >> + - const: core >> + - const: sys >> + - const: mem >> + - const: hyd >> + >> + sgx-supply: true >> + >> + power-domains: >> + maxItems: 1 >> + >> + resets: >> + maxItems: 1 >> + >> +required: >> + - compatible >> + - reg >> + - interrupts > > By not making 'clocks' required you make it possible to create broken bindings; according to your schema, a GPU node without a 'clocks' for the JZ4780 would be perfectly valid. Yes. But it will never pass a test with real hardware. So it can't be omitted anyways. On a more general thought, this argument holds for any optional property. So it is not specific to clocks. Since the reg address values are also never specified you can still create broken bindings. Or by connecting the wrong clock. So the ways to create broken bindings are numerous. I also assume that SGX integrators are not beginners and do you think they need to find out through a make dt_binding_check dtbs_check that they should define a clock? based on *assumptions* we do without having access to all systems? IMHO the bindings documentation is a documentation. So it needs to be helpful but not perfect. Formalizing all corner cases in a bindings document (just because we can since .yaml was introduced) is IMHO overkill. In times before the introduction of more formal .yaml I think we would not even have considered this for a comment in the bindings.txt. > It's possible to forbid the presence of the 'clocks' property on some implementations, and require it on others. To be precise we have to specify the exact number of clocks (between 0 and 4) for every architecture. This also contradicts my dream to get rid of the architecture specific components in the long run. My dream (because I can't tell how it can be done) is that we can one day develop something which just needs compatible = img,530 or imp,540 or img,544. Then we can't make the number clocks depend on the implementation any more. > See how it's done for instance on Documentation/devicetree/bindings/serial/samsung_uart.yaml. Yes I know the design pattern, but I wonder if such a move makes the whole thing even less maintainable. Assume we have finished DTS for some SoC. Then these DTS have been tested on real hardware and are working. Clocks are there where needed and missing where not. We may now forbid or not forbid them for some implementations in the bindings.yaml but the result of dtbs_check won't change! Because they are tested and working and the bindings.yaml has been adapted to the result. So we have just duplicated something for no practical benefit. Next, assume there is coming support for more and more new SoC. Then, developers not only have to figure out which clocks they need in the DTS but they also have to add a patch to the implementation specific part of the bindings.yaml to clearly define exactly the same what they already have written into their .dts (the clocks are either there for the of_node or they are not). So again the rules are for no benefit, since a new SoC is introduced exactly once. And tested if it works. And if it is there, it will stay as it is. It is just work for maintainers to review that patch as well. It boils down to the question if we need to formalize the rule how a working DTS was derived. Or just have a working DTS and not formalize everything. So IMHO carrying along such a detail (forbid clocks on some architectures) is nice to have (and fun to learn the .yaml thing) but not of benefit for anyone. Not for the DTS developer nor for the maintainers nor for the users of a Linux kernel. "Keep it simple" is always a good rule for maintainability. In summary I don't see a good reason to follow this in v8. But you could add it by a separate patch later if the DTS have been reviewed and agreed. BR and thanks, Nikolaus
Hi Nikolaus, Le sam. 2 mai 2020 à 22:26, H. Nikolaus Schaller <hns@goldelico.com> a écrit : > Hi Paul, > >> Am 26.04.2020 um 15:11 schrieb Paul Cercueil <paul@crapouillou.net>: >> >> Hi Nikolaus, >> >> Le ven. 24 avril 2020 à 22:34, H. Nikolaus Schaller >> <hns@goldelico.com> a écrit : >>> The Imagination PVR/SGX GPU is part of several SoC from >>> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, >>> Allwinner A83 and others. >>> With this binding, we describe how the SGX processor is >>> interfaced to the SoC (registers and interrupt). >>> The interface also consists of clocks, reset, power but >>> information from data sheets is vague and some SoC integrators >>> (TI) deciced to use a PRCM wrapper (ti,sysc) which does >>> all clock, reset and power-management through registers >>> outside of the sgx register block. >>> Therefore all these properties are optional. >>> Tested by make dt_binding_check >>> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> >>> --- >>> .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 >>> ++++++++++++++++++ >>> 1 file changed, 150 insertions(+) >>> create mode 100644 >>> Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >>> diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >>> b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >>> new file mode 100644 >>> index 000000000000..33a9c4c6e784 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml >>> @@ -0,0 +1,150 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Imagination PVR/SGX GPU >>> + >>> +maintainers: >>> + - H. Nikolaus Schaller <hns@goldelico.com> >>> + >>> +description: |+ >>> + This binding describes the Imagination SGX5 series of 3D >>> accelerators which >>> + are found in several different SoC like TI OMAP, Sitara, >>> Ingenic JZ4780, >>> + Allwinner A83, and Intel Poulsbo and CedarView and more. >>> + >>> + For an extensive list see: >>> https://en.wikipedia.org/wiki/PowerVR#Implementations >>> + >>> + The SGX node is usually a child node of some DT node belonging >>> to the SoC >>> + which handles clocks, reset and general address space mapping >>> of the SGX >>> + register area. If not, an optional clock can be specified here. >>> + >>> +properties: >>> + $nodename: >>> + pattern: '^gpu@[a-f0-9]+$' >>> + compatible: >>> + oneOf: >>> + - description: SGX530-121 based SoC >>> + items: >>> + - enum: >>> + - ti,omap3-sgx530-121 # BeagleBoard A/B/C, >>> OpenPandora 600MHz and similar >>> + - const: img,sgx530-121 >>> + - const: img,sgx530 >>> + >>> + - description: SGX530-125 based SoC >>> + items: >>> + - enum: >>> + - ti,am3352-sgx530-125 # BeagleBone Black >>> + - ti,am3517-sgx530-125 >>> + - ti,am4-sgx530-125 >>> + - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, >>> OpenPandora 1GHz and similar >>> + - ti,ti81xx-sgx530-125 >>> + - const: ti,omap3-sgx530-125 >>> + - const: img,sgx530-125 >>> + - const: img,sgx530 >>> + >>> + - description: SGX535-116 based SoC >>> + items: >>> + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx >>> + - const: img,sgx535-116 >>> + - const: img,sgx535 >>> + >>> + - description: SGX540-116 based SoC >>> + items: >>> + - const: intel,medfield-gma-sgx540 # Atom Z24xx >>> + - const: img,sgx540-116 >>> + - const: img,sgx540 >>> + >>> + - description: SGX540-120 based SoC >>> + items: >>> + - enum: >>> + - samsung,s5pv210-sgx540-120 >>> + - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and >>> similar >>> + - const: img,sgx540-120 >>> + - const: img,sgx540 >>> + >>> + - description: SGX540-130 based SoC >>> + items: >>> + - enum: >>> + - ingenic,jz4780-sgx540-130 # CI20 >>> + - const: img,sgx540-130 >>> + - const: img,sgx540 >>> + >>> + - description: SGX544-112 based SoC >>> + items: >>> + - const: ti,omap4470-sgx544-112 >>> + - const: img,sgx544-112 >>> + - const: img,sgx544 >>> + >>> + - description: SGX544-115 based SoC >>> + items: >>> + - enum: >>> + - allwinner,sun8i-a31-sgx544-115 >>> + - allwinner,sun8i-a31s-sgx544-115 >>> + - allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 >>> (Allwinner A83T) and similar >>> + - const: img,sgx544-115 >>> + - const: img,sgx544 >>> + >>> + - description: SGX544-116 based SoC >>> + items: >>> + - enum: >>> + - ti,dra7-sgx544-116 # DRA7 >>> + - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and >>> similar >>> + - const: img,sgx544-116 >>> + - const: img,sgx544 >>> + >>> + - description: SGX545 based SoC >>> + items: >>> + - const: intel,cedarview-gma3600-sgx545 # Atom N2600, >>> D2500 >>> + - const: img,sgx545-116 >>> + - const: img,sgx545 >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + interrupts: >>> + maxItems: 1 >>> + >>> + interrupt-names: >>> + maxItems: 1 >>> + items: >>> + - const: sgx >>> + >>> + clocks: >>> + maxItems: 4 >>> + >>> + clock-names: >>> + maxItems: 4 >>> + items: >>> + - const: core >>> + - const: sys >>> + - const: mem >>> + - const: hyd >>> + >>> + sgx-supply: true >>> + >>> + power-domains: >>> + maxItems: 1 >>> + >>> + resets: >>> + maxItems: 1 >>> + >>> +required: >>> + - compatible >>> + - reg >>> + - interrupts >> >> By not making 'clocks' required you make it possible to create >> broken bindings; according to your schema, a GPU node without a >> 'clocks' for the JZ4780 would be perfectly valid. > > Yes. But it will never pass a test with real hardware. So it can't be > omitted anyways. > > On a more general thought, this argument holds for any optional > property. So it is not specific to clocks. Since the reg address > values are also never specified you can still create broken bindings. > Or by connecting the wrong clock. So the ways to create broken > bindings are numerous. > > I also assume that SGX integrators are not beginners and do you think > they need to find out through a make dt_binding_check dtbs_check that > they should define a clock? based on *assumptions* we do without > having access to all systems? > > IMHO the bindings documentation is a documentation. So it needs to be > helpful but not perfect. Formalizing all corner cases in a bindings > document (just because we can since .yaml was introduced) is IMHO > overkill. > > In times before the introduction of more formal .yaml I think we > would not even have considered this for a comment in the bindings.txt. > >> It's possible to forbid the presence of the 'clocks' property on >> some implementations, and require it on others. > > To be precise we have to specify the exact number of clocks (between > 0 and 4) for every architecture. > > This also contradicts my dream to get rid of the architecture > specific components in the long run. My dream (because I can't tell > how it can be done) is that we can one day develop something which > just needs compatible = img,530 or imp,540 or img,544. Then we can't > make the number clocks depend on the implementation any more. As we said before, the number of clocks is a property of the GPU and *not* its integration into the SoC. So you would *not* have a number of clocks between 0 and 4. You get either 0, or 4, depending on whether or not you have a wrapper. >> See how it's done for instance on >> Documentation/devicetree/bindings/serial/samsung_uart.yaml. > > Yes I know the design pattern, but I wonder if such a move makes the > whole thing even less maintainable. > > Assume we have finished DTS for some SoC. Then these DTS have been > tested on real hardware and are working. Clocks are there where > needed and missing where not. We may now forbid or not forbid them > for some implementations in the bindings.yaml but the result of > dtbs_check won't change! Because they are tested and working and the > bindings.yaml has been adapted to the result. So we have just > duplicated something for no practical benefit. > > Next, assume there is coming support for more and more new SoC. Then, > developers not only have to figure out which clocks they need in the > DTS but they also have to add a patch to the implementation specific > part of the bindings.yaml to clearly define exactly the same what > they already have written into their .dts (the clocks are either > there for the of_node or they are not). So again the rules are for no > benefit, since a new SoC is introduced exactly once. And tested if it > works. And if it is there, it will stay as it is. It is just work for > maintainers to review that patch as well. If you add support for a new SoC, you'd still need to modify the binding to add the compatible string. So the argument of "more work" is moot. -Paul > It boils down to the question if we need to formalize the rule how a > working DTS was derived. Or just have a working DTS and not formalize > everything. > > So IMHO carrying along such a detail (forbid clocks on some > architectures) is nice to have (and fun to learn the .yaml thing) but > not of benefit for anyone. Not for the DTS developer nor for the > maintainers nor for the users of a Linux kernel. "Keep it simple" is > always a good rule for maintainability. > > In summary I don't see a good reason to follow this in v8. But you > could add it by a separate patch later if the DTS have been reviewed > and agreed. > > BR and thanks, > Nikolaus >
Hi Paul, > Am 03.05.2020 um 14:52 schrieb Paul Cercueil <paul@crapouillou.net>: > >>> It's possible to forbid the presence of the 'clocks' property on some implementations, and require it on others. >> To be precise we have to specify the exact number of clocks (between 0 and 4) for every architecture. >> This also contradicts my dream to get rid of the architecture specific components in the long run. My dream (because I can't tell how it can be done) is that we can one day develop something which just needs compatible = img,530 or imp,540 or img,544. Then we can't make the number clocks depend on the implementation any more. > > As we said before, the number of clocks is a property of the GPU and *not* its integration into the SoC. Well, it is a not very well documented property of the GPU. We have no data sheet of the standalone GPU. Only several SoC data sheets which give some indications. It appears as if some sgx5xx versions have 3 clocks and some have 4. So you are right, the number of clocks depends on the sgx5xx version and that could be made dependent in the bindings (if necessary). > > So you would *not* have a number of clocks between 0 and 4. You get either 0, or 4, depending on whether or not you have a wrapper. I think this is contradicting your previous sentence. If the number of clocks is a property of the GPU and not the integration it must also not depend on whether there is a wrapper. I.e. it must be a constant for any type of integration. The really correct variant would be to always make the SoC integration (wrapper) a separate subsystem (because it is never part of the SGX core but some interface bus) and clock provider and connect it explicitly to the clock inputs. To be clear: I am not at all against describing the clocks. I just doubt that the time we invest into discussing on this level of detail and adding conditional clock requirements is worth the result. IMHO the bindings and .dts do not become better by describing them in more detail than just "optional". It just takes our time from contributing to other subsystems. > > >>> See how it's done for instance on Documentation/devicetree/bindings/serial/samsung_uart.yaml. >> Yes I know the design pattern, but I wonder if such a move makes the whole thing even less maintainable. >> Assume we have finished DTS for some SoC. Then these DTS have been tested on real hardware and are working. Clocks are there where needed and missing where not. We may now forbid or not forbid them for some implementations in the bindings.yaml but the result of dtbs_check won't change! Because they are tested and working and the bindings.yaml has been adapted to the result. So we have just duplicated something for no practical benefit. >> Next, assume there is coming support for more and more new SoC. Then, developers not only have to figure out which clocks they need in the DTS but they also have to add a patch to the implementation specific part of the bindings.yaml to clearly define exactly the same what they already have written into their .dts (the clocks are either there for the of_node or they are not). So again the rules are for no benefit, since a new SoC is introduced exactly once. And tested if it works. And if it is there, it will stay as it is. It is just work for maintainers to review that patch as well. > > If you add support for a new SoC, you'd still need to modify the binding to add the compatible string. So the argument of "more work" is moot. Agreed, I forgot this aspect. Nevertheless, it is easier to review a new compatible string than a new clock number rule (question: how do you practically review this? By looking if it does match the DTS?). We have to add the compatible string as long as we need to have the SoC name in the compatible string (which as said is my dream to get rid of in far future). If we could get rid of it, there won't be a change any more. By just taking "img,sgx544" into a new SoC. The change would be moved into SoC specific wrappers. In such an ideal world, we would explicitly describe the wrappers as separate DT nodes. Even if they have no explicit driver (e.g. by some simple-pm-bus). PRCM,bus, Processor <<---->> Wrapper <<----->> SGX ti,... ti,sysc img,sgx530 img,... simple-bus img,sgx540 samsung,... ... img,sgx544 other, other,gpu-wrapper img,... But this IMHO correct proposal was already rejected. So at the moment we are circling around several proposals because none can fulfill all requirements. Therefore my attempt to solve the gordian knot is to make clocks generally optional. This keeps the bindings simple but not generally wrong. And since the DTS are not only tested against bindings.yaml but on real hardware, the omission to enforce a specific number of clocks doesn't harm anyone. As said it is impossible to get the SGX running without defining the correct clocks (whether they are enforced by bindings.yaml or not). BR and thanks, Nikolaus
Le dim. 3 mai 2020 à 15:31, H. Nikolaus Schaller <hns@goldelico.com> a écrit : > Hi Paul, > >> Am 03.05.2020 um 14:52 schrieb Paul Cercueil <paul@crapouillou.net>: >> >>>> It's possible to forbid the presence of the 'clocks' property on >>>> some implementations, and require it on others. >>> To be precise we have to specify the exact number of clocks >>> (between 0 and 4) for every architecture. >>> This also contradicts my dream to get rid of the architecture >>> specific components in the long run. My dream (because I can't tell >>> how it can be done) is that we can one day develop something which >>> just needs compatible = img,530 or imp,540 or img,544. Then we >>> can't make the number clocks depend on the implementation any more. >> >> As we said before, the number of clocks is a property of the GPU >> and *not* its integration into the SoC. > > Well, it is a not very well documented property of the GPU. We have > no data sheet of the standalone GPU. Only several SoC data sheets > which give some indications. Maybe we can nicely ask them? I expect Paul Burton to have some contacts at ImgTec. Asking for a doc would be too much, but maybe they can help a bit with the DT bindings. > It appears as if some sgx5xx versions have 3 clocks and some have 4. > So you are right, the number of clocks depends on the sgx5xx version > and that could be made dependent in the bindings (if necessary). > >> >> So you would *not* have a number of clocks between 0 and 4. You get >> either 0, or 4, depending on whether or not you have a wrapper. > > I think this is contradicting your previous sentence. If the number > of clocks is a property of the GPU and not the integration it must > also not depend on whether there is a wrapper. I.e. it must be a > constant for any type of integration. Well, I expected all SGX versions to have 4 clocks. If some SGX versions have 3 clocks, and others have 4 clocks, it's still OK as long as the number of clocks is enforced, so that all implementations of a given SGX core will have to use the same number of clocks. > The really correct variant would be to always make the SoC > integration (wrapper) a separate subsystem (because it is never part > of the SGX core but some interface bus) and clock provider and > connect it explicitly to the clock inputs. About the wrapper... I don't really know how it's done there. But you could very well pass all clocks unconditionally to the SGX node, even if it's inside a wrapper. The wrapper itself probably needs only one clock, the one that allows it to access its registers. > To be clear: I am not at all against describing the clocks. I just > doubt that the time we invest into discussing on this level of detail > and adding conditional clock requirements is worth the result. IMHO > the bindings and .dts do not become better by describing them in more > detail than just "optional". It just takes our time from contributing > to other subsystems. > You have a new SoC with a SGX, and you only need to enable one clock to get it to work. So you create a devicetree node which receives only one clock. Turns out, that the bootloader was enabling the other 3 clocks, and since the last release, it doesn't anymore. You're left with having to support a broken devicetree. That's the kind of problem that can be easily avoided by enforcing the number of clocks that have to be provided. >> >> >>>> See how it's done for instance on >>>> Documentation/devicetree/bindings/serial/samsung_uart.yaml. >>> Yes I know the design pattern, but I wonder if such a move makes >>> the whole thing even less maintainable. >>> Assume we have finished DTS for some SoC. Then these DTS have been >>> tested on real hardware and are working. Clocks are there where >>> needed and missing where not. We may now forbid or not forbid them >>> for some implementations in the bindings.yaml but the result of >>> dtbs_check won't change! Because they are tested and working and >>> the bindings.yaml has been adapted to the result. So we have just >>> duplicated something for no practical benefit. >>> Next, assume there is coming support for more and more new SoC. >>> Then, developers not only have to figure out which clocks they need >>> in the DTS but they also have to add a patch to the implementation >>> specific part of the bindings.yaml to clearly define exactly the >>> same what they already have written into their .dts (the clocks are >>> either there for the of_node or they are not). So again the rules >>> are for no benefit, since a new SoC is introduced exactly once. And >>> tested if it works. And if it is there, it will stay as it is. It >>> is just work for maintainers to review that patch as well. >> >> If you add support for a new SoC, you'd still need to modify the >> binding to add the compatible string. So the argument of "more work" >> is moot. > > Agreed, I forgot this aspect. Nevertheless, it is easier to review a > new compatible string than a new clock number rule (question: how do > you practically review this? By looking if it does match the DTS?). > > We have to add the compatible string as long as we need to have the > SoC name in the compatible string (which as said is my dream to get > rid of in far future). If we could get rid of it, there won't be a > change any more. By just taking "img,sgx544" into a new SoC. The > change would be moved into SoC specific wrappers. In such an ideal > world, we would explicitly describe the wrappers as separate DT > nodes. Even if they have no explicit driver (e.g. by some > simple-pm-bus). What's wrong with having the SoC name in the compatible string? You cannot use just a "img,sgx544" compatible string, as then you would assume that the same SGX version in (e.g.) an Ingenic or a Omap SoC is the exact same. This may actually be true. But the moment you discover even a tiny thing that needs to be handled differently, you wouldn't have the possibility to do so. > PRCM,bus, > Processor <<---->> Wrapper <<----->> SGX > ti,... ti,sysc img,sgx530 > img,... simple-bus img,sgx540 > samsung,... ... img,sgx544 > other, other,gpu-wrapper img,... > > But this IMHO correct proposal was already rejected. > > So at the moment we are circling around several proposals because > none can fulfill all requirements. > > Therefore my attempt to solve the gordian knot is to make clocks > generally optional. This keeps the bindings simple but not generally > wrong. And since the DTS are not only tested against bindings.yaml > but on real hardware, the omission to enforce a specific number of > clocks doesn't harm anyone. As said it is impossible to get the SGX > running without defining the correct clocks (whether they are > enforced by bindings.yaml or not). That's what I tried to explain above. You'd be able to get the SGX to work without a single clock in devicetree. That doesn't mean it should be allowed. Cheers, -Paul
* Paul Cercueil <paul@crapouillou.net> [200503 14:19]: > You have a new SoC with a SGX, and you only need to enable one clock to get > it to work. So you create a devicetree node which receives only one clock. > > Turns out, that the bootloader was enabling the other 3 clocks, and since > the last release, it doesn't anymore. You're left with having to support a > broken devicetree. > > That's the kind of problem that can be easily avoided by enforcing the > number of clocks that have to be provided. The number of clocks depends on how it's wired for the SoC. On omaps, there's are no controls for additinoal SGX clocks. Sure some of the clocks may be routed to multple places internally by the wrapper module. But we have no control over that. If we wanted to specify just the "fck" clock on omaps, then we can do it with something like this: allOf: - if: properites: compatible: enum: - "ti,omap4-sgx544-112" - "ti,omap5-sgx544-116" - "ti,dra7-sgx544-116" then: properties: clocks: minItems: 1 maxItems: 1 clock-names: const: fck required: - clocks - clock-names There's no need for the SGX driver to toggle the "fck" here, it's all done by PM runtime alreaedy so we would be just tweaking the usage count for it. But hey, showing the clock rate might be nice. Or maybe we want to at some point scale it, so no problem specifying it. For omap3, we should then specify "fck" and "ick". On omap4 and later, there's no separate control over the "ick". Then for the other SoCs, you can specify whatever clocks you need there. Regards, Tony
Hi Paul and Paul, > Am 03.05.2020 um 16:18 schrieb Paul Cercueil <paul@crapouillou.net>: > > > > Le dim. 3 mai 2020 à 15:31, H. Nikolaus Schaller <hns@goldelico.com> a écrit : >> Hi Paul, >>> Am 03.05.2020 um 14:52 schrieb Paul Cercueil <paul@crapouillou.net>: >>>>> It's possible to forbid the presence of the 'clocks' property on some implementations, and require it on others. >>>> To be precise we have to specify the exact number of clocks (between 0 and 4) for every architecture. >>>> This also contradicts my dream to get rid of the architecture specific components in the long run. My dream (because I can't tell how it can be done) is that we can one day develop something which just needs compatible = img,530 or imp,540 or img,544. Then we can't make the number clocks depend on the implementation any more. >>> As we said before, the number of clocks is a property of the GPU and *not* its integration into the SoC. >> Well, it is a not very well documented property of the GPU. We have no data sheet of the standalone GPU. Only several SoC data sheets which give some indications. > > Maybe we can nicely ask them? There is some (old) answer here: https://github.com/MIPS/CI20_linux/blob/ci20-v3.18/arch/mips/boot/dts/jz4780.dtsi#L63 > I expect Paul Burton to have some contacts at ImgTec. Asking for a doc would be too much, but maybe they can help a bit with the DT bindings. Good idea! It is definitively worth to try. Therefore I have moved him from CC: to To: > >> It appears as if some sgx5xx versions have 3 clocks and some have 4. So you are right, the number of clocks depends on the sgx5xx version and that could be made dependent in the bindings (if necessary). >>> So you would *not* have a number of clocks between 0 and 4. You get either 0, or 4, depending on whether or not you have a wrapper. >> I think this is contradicting your previous sentence. If the number of clocks is a property of the GPU and not the integration it must also not depend on whether there is a wrapper. I.e. it must be a constant for any type of integration. > > Well, I expected all SGX versions to have 4 clocks. > > If some SGX versions have 3 clocks, and others have 4 clocks, it's still OK as long as the number of clocks is enforced, so that all implementations of a given SGX core will have to use the same number of clocks. > >> The really correct variant would be to always make the SoC integration (wrapper) a separate subsystem (because it is never part of the SGX core but some interface bus) and clock provider and connect it explicitly to the clock inputs. > > About the wrapper... I don't really know how it's done there. But you could very well pass all clocks unconditionally to the SGX node, even if it's inside a wrapper. > The wrapper itself probably needs only one clock, the one that allows it to access its registers. > >> To be clear: I am not at all against describing the clocks. I just doubt that the time we invest into discussing on this level of detail and adding conditional clock requirements is worth the result. IMHO the bindings and .dts do not become better by describing them in more detail than just "optional". It just takes our time from contributing to other subsystems. > > You have a new SoC with a SGX, and you only need to enable one clock to get it to work. So you create a devicetree node which receives only one clock. > > Turns out, that the bootloader was enabling the other 3 clocks, Does it? I haven't seen such boot loaders. Usually they bring up only the core and e.g. mmc to be able to boot. > and since the last release, it doesn't anymore. You're left with having to support a broken devicetree. > > That's the kind of problem that can be easily avoided by enforcing the number of clocks that have to be provided. >>>>> See how it's done for instance on Documentation/devicetree/bindings/serial/samsung_uart.yaml. >>>> Yes I know the design pattern, but I wonder if such a move makes the whole thing even less maintainable. >>>> Assume we have finished DTS for some SoC. Then these DTS have been tested on real hardware and are working. Clocks are there where needed and missing where not. We may now forbid or not forbid them for some implementations in the bindings.yaml but the result of dtbs_check won't change! Because they are tested and working and the bindings.yaml has been adapted to the result. So we have just duplicated something for no practical benefit. >>>> Next, assume there is coming support for more and more new SoC. Then, developers not only have to figure out which clocks they need in the DTS but they also have to add a patch to the implementation specific part of the bindings.yaml to clearly define exactly the same what they already have written into their .dts (the clocks are either there for the of_node or they are not). So again the rules are for no benefit, since a new SoC is introduced exactly once. And tested if it works. And if it is there, it will stay as it is. It is just work for maintainers to review that patch as well. >>> If you add support for a new SoC, you'd still need to modify the binding to add the compatible string. So the argument of "more work" is moot. >> Agreed, I forgot this aspect. Nevertheless, it is easier to review a new compatible string than a new clock number rule (question: how do you practically review this? By looking if it does match the DTS?). >> We have to add the compatible string as long as we need to have the SoC name in the compatible string (which as said is my dream to get rid of in far future). If we could get rid of it, there won't be a change any more. By just taking "img,sgx544" into a new SoC. The change would be moved into SoC specific wrappers. In such an ideal world, we would explicitly describe the wrappers as separate DT nodes. Even if they have no explicit driver (e.g. by some simple-pm-bus). > > What's wrong with having the SoC name in the compatible string? I'd say it should be avoided if possible. But you give a good hint and a little research shows some examples having the SoC name in the compatible string: musb, dwc2, dwc3. > > You cannot use just a "img,sgx544" compatible string, as then you would assume that the same SGX version in (e.g.) an Ingenic or a Omap SoC is the exact same. This may actually be true. Yes. That is the assumption and I have not seen any hints for the opposite in the pvrsrvkm sources. They only differentiate the SoC integration (clocks, reset) but not in the SGX operation (memory mapping, communication with firmware) itself. So the differences could easily be factored out into a wrapper driver. > But the moment you discover even a tiny thing that needs to be handled differently, you wouldn't have the possibility to do so. You would still have the possibility. An SGX driver can instead of differentiating by its own compatible string table look for the wrapper or SoC compatible string to find out where the sgx is integrated to. It is just simpler to do if we have the combined soc+sgx versions. And at the moment we even compile separate kernel modules from the same source. > >> PRCM,bus, >> Processor <<---->> Wrapper <<----->> SGX >> ti,... ti,sysc img,sgx530 >> img,... simple-bus img,sgx540 >> samsung,... ... img,sgx544 >> other, other,gpu-wrapper img,... >> But this IMHO correct proposal was already rejected. >> So at the moment we are circling around several proposals because none can fulfill all requirements. >> Therefore my attempt to solve the gordian knot is to make clocks generally optional. This keeps the bindings simple but not generally wrong. And since the DTS are not only tested against bindings.yaml but on real hardware, the omission to enforce a specific number of clocks doesn't harm anyone. As said it is impossible to get the SGX running without defining the correct clocks (whether they are enforced by bindings.yaml or not). > > That's what I tried to explain above. You'd be able to get the SGX to work without a single clock in devicetree. That doesn't mean it should be allowed. > > Cheers, > -Paul BR and thanks, Nikolaus
On Fri, Apr 24, 2020 at 10:34:04PM +0200, H. Nikolaus Schaller wrote: > The Imagination PVR/SGX GPU is part of several SoC from > multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, > Allwinner A83 and others. > > With this binding, we describe how the SGX processor is > interfaced to the SoC (registers and interrupt). > > The interface also consists of clocks, reset, power but > information from data sheets is vague and some SoC integrators > (TI) deciced to use a PRCM wrapper (ti,sysc) which does > all clock, reset and power-management through registers > outside of the sgx register block. > > Therefore all these properties are optional. > > Tested by make dt_binding_check > > Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> > --- > .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++++++++++++++++++ > 1 file changed, 150 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > > diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > new file mode 100644 > index 000000000000..33a9c4c6e784 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml > @@ -0,0 +1,150 @@ > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Imagination PVR/SGX GPU > + > +maintainers: > + - H. Nikolaus Schaller <hns@goldelico.com> > + > +description: |+ > + This binding describes the Imagination SGX5 series of 3D accelerators which > + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780, > + Allwinner A83, and Intel Poulsbo and CedarView and more. > + > + For an extensive list see: https://en.wikipedia.org/wiki/PowerVR#Implementations > + > + The SGX node is usually a child node of some DT node belonging to the SoC > + which handles clocks, reset and general address space mapping of the SGX > + register area. If not, an optional clock can be specified here. > + > +properties: > + $nodename: > + pattern: '^gpu@[a-f0-9]+$' > + compatible: > + oneOf: > + - description: SGX530-121 based SoC > + items: > + - enum: > + - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar Should be indented 2 more here and elsewhere where you have a list under a list. > + - const: img,sgx530-121 > + - const: img,sgx530 > + > + - description: SGX530-125 based SoC > + items: > + - enum: > + - ti,am3352-sgx530-125 # BeagleBone Black > + - ti,am3517-sgx530-125 > + - ti,am4-sgx530-125 > + - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz and similar > + - ti,ti81xx-sgx530-125 > + - const: ti,omap3-sgx530-125 > + - const: img,sgx530-125 > + - const: img,sgx530 > + > + - description: SGX535-116 based SoC > + items: > + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx > + - const: img,sgx535-116 > + - const: img,sgx535 > + > + - description: SGX540-116 based SoC > + items: > + - const: intel,medfield-gma-sgx540 # Atom Z24xx > + - const: img,sgx540-116 > + - const: img,sgx540 > + > + - description: SGX540-120 based SoC > + items: > + - enum: > + - samsung,s5pv210-sgx540-120 > + - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar > + - const: img,sgx540-120 > + - const: img,sgx540 > + > + - description: SGX540-130 based SoC > + items: > + - enum: > + - ingenic,jz4780-sgx540-130 # CI20 > + - const: img,sgx540-130 > + - const: img,sgx540 > + > + - description: SGX544-112 based SoC > + items: > + - const: ti,omap4470-sgx544-112 > + - const: img,sgx544-112 > + - const: img,sgx544 > + > + - description: SGX544-115 based SoC > + items: > + - enum: > + - allwinner,sun8i-a31-sgx544-115 > + - allwinner,sun8i-a31s-sgx544-115 > + - allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 (Allwinner A83T) and similar > + - const: img,sgx544-115 > + - const: img,sgx544 > + > + - description: SGX544-116 based SoC > + items: > + - enum: > + - ti,dra7-sgx544-116 # DRA7 > + - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar > + - const: img,sgx544-116 > + - const: img,sgx544 > + > + - description: SGX545 based SoC > + items: > + - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500 > + - const: img,sgx545-116 > + - const: img,sgx545 > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + interrupt-names: > + maxItems: 1 > + items: > + - const: sgx > + > + clocks: > + maxItems: 4 > + > + clock-names: > + maxItems: 4 > + items: > + - const: core > + - const: sys > + - const: mem > + - const: hyd > + > + sgx-supply: true > + > + power-domains: > + maxItems: 1 > + > + resets: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + > +additionalProperties: false > + > +examples: > + - |+ > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + > + gpu: gpu@fe00 { > + compatible = "ti,omap5-sgx544-116", "img,sgx544-116", "img,sgx544"; > + reg = <0xfe00 0x200>; > + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > + }; > + > +... > -- > 2.25.1 >
Hi Paul & Paul, > Am 03.05.2020 um 18:41 schrieb H. Nikolaus Schaller <hns@goldelico.com>: > > Hi Paul and Paul, > >> Am 03.05.2020 um 16:18 schrieb Paul Cercueil <paul@crapouillou.net>: >> >> >> >> Le dim. 3 mai 2020 à 15:31, H. Nikolaus Schaller <hns@goldelico.com> a écrit : >>> Hi Paul, >>>> Am 03.05.2020 um 14:52 schrieb Paul Cercueil <paul@crapouillou.net>: >>>>>> It's possible to forbid the presence of the 'clocks' property on some implementations, and require it on others. >>>>> To be precise we have to specify the exact number of clocks (between 0 and 4) for every architecture. >>>>> This also contradicts my dream to get rid of the architecture specific components in the long run. My dream (because I can't tell how it can be done) is that we can one day develop something which just needs compatible = img,530 or imp,540 or img,544. Then we can't make the number clocks depend on the implementation any more. >>>> As we said before, the number of clocks is a property of the GPU and *not* its integration into the SoC. >>> Well, it is a not very well documented property of the GPU. We have no data sheet of the standalone GPU. Only several SoC data sheets which give some indications. >> >> Maybe we can nicely ask them? > > There is some (old) answer here: > > https://github.com/MIPS/CI20_linux/blob/ci20-v3.18/arch/mips/boot/dts/jz4780.dtsi#L63 > >> I expect Paul Burton to have some contacts at ImgTec. Asking for a doc would be too much, but maybe they can help a bit with the DT bindings. > > Good idea! It is definitively worth to try. Therefore I have moved him from CC: to To: Do we already have an idea if we can get into contact and get help from ImgTec for this topic or if we have to live with what we have? BR and thanks, Nikolaus
Hi Tony, > Am 03.05.2020 um 17:01 schrieb Tony Lindgren <tony@atomide.com>: > > * Paul Cercueil <paul@crapouillou.net> [200503 14:19]: >> You have a new SoC with a SGX, and you only need to enable one clock to get >> it to work. So you create a devicetree node which receives only one clock. >> >> Turns out, that the bootloader was enabling the other 3 clocks, and since >> the last release, it doesn't anymore. You're left with having to support a >> broken devicetree. >> >> That's the kind of problem that can be easily avoided by enforcing the >> number of clocks that have to be provided. > > The number of clocks depends on how it's wired for the SoC. > > On omaps, there's are no controls for additinoal SGX clocks. Sure some > of the clocks may be routed to multple places internally by the wrapper > module. But we have no control over that. > > If we wanted to specify just the "fck" clock on omaps, then we can > do it with something like this: > > allOf: > - if: > properites: > compatible: > enum: > - "ti,omap4-sgx544-112" > - "ti,omap5-sgx544-116" > - "ti,dra7-sgx544-116" > then: > properties: > clocks: > minItems: 1 > maxItems: 1 > > clock-names: > const: fck > > required: > - clocks > - clock-names will add to v8 of this series as a separate patch on top of the general one. This should make it easier to have a focussed discussion and revert/bisect if something goes wrong. BR and thanks, Nikolaus
> Am 05.05.2020 um 17:53 schrieb Rob Herring <robh@kernel.org>: > > On Fri, Apr 24, 2020 at 10:34:04PM +0200, H. Nikolaus Schaller wrote: >> The Imagination PVR/SGX GPU is part of several SoC from >> multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, >> Allwinner A83 and others. >> >> With this binding, we describe how the SGX processor is >> interfaced to the SoC (registers and interrupt). >> >> The interface also consists of clocks, reset, power but >> information from data sheets is vague and some SoC integrators >> (TI) deciced to use a PRCM wrapper (ti,sysc) which does >> all clock, reset and power-management through registers >> outside of the sgx register block. >> >> Therefore all these properties are optional. >> >> Tested by make dt_binding_check >> >> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> >> --- >> .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++++++++++++++++++ >> 1 file changed, 150 insertions(+) >> + oneOf: >> + - description: SGX530-121 based SoC >> + items: >> + - enum: >> + - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar > > Should be indented 2 more here and elsewhere where you have a list > under a list. added for patch v8 series. BR and thanks, Nikolaus
diff --git a/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml new file mode 100644 index 000000000000..33a9c4c6e784 --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/img,pvrsgx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Imagination PVR/SGX GPU + +maintainers: + - H. Nikolaus Schaller <hns@goldelico.com> + +description: |+ + This binding describes the Imagination SGX5 series of 3D accelerators which + are found in several different SoC like TI OMAP, Sitara, Ingenic JZ4780, + Allwinner A83, and Intel Poulsbo and CedarView and more. + + For an extensive list see: https://en.wikipedia.org/wiki/PowerVR#Implementations + + The SGX node is usually a child node of some DT node belonging to the SoC + which handles clocks, reset and general address space mapping of the SGX + register area. If not, an optional clock can be specified here. + +properties: + $nodename: + pattern: '^gpu@[a-f0-9]+$' + compatible: + oneOf: + - description: SGX530-121 based SoC + items: + - enum: + - ti,omap3-sgx530-121 # BeagleBoard A/B/C, OpenPandora 600MHz and similar + - const: img,sgx530-121 + - const: img,sgx530 + + - description: SGX530-125 based SoC + items: + - enum: + - ti,am3352-sgx530-125 # BeagleBone Black + - ti,am3517-sgx530-125 + - ti,am4-sgx530-125 + - ti,omap3-sgx530-125 # BeagleBoard XM, GTA04, OpenPandora 1GHz and similar + - ti,ti81xx-sgx530-125 + - const: ti,omap3-sgx530-125 + - const: img,sgx530-125 + - const: img,sgx530 + + - description: SGX535-116 based SoC + items: + - const: intel,poulsbo-gma500-sgx535 # Atom Z5xx + - const: img,sgx535-116 + - const: img,sgx535 + + - description: SGX540-116 based SoC + items: + - const: intel,medfield-gma-sgx540 # Atom Z24xx + - const: img,sgx540-116 + - const: img,sgx540 + + - description: SGX540-120 based SoC + items: + - enum: + - samsung,s5pv210-sgx540-120 + - ti,omap4-sgx540-120 # Pandaboard, Pandaboard ES and similar + - const: img,sgx540-120 + - const: img,sgx540 + + - description: SGX540-130 based SoC + items: + - enum: + - ingenic,jz4780-sgx540-130 # CI20 + - const: img,sgx540-130 + - const: img,sgx540 + + - description: SGX544-112 based SoC + items: + - const: ti,omap4470-sgx544-112 + - const: img,sgx544-112 + - const: img,sgx544 + + - description: SGX544-115 based SoC + items: + - enum: + - allwinner,sun8i-a31-sgx544-115 + - allwinner,sun8i-a31s-sgx544-115 + - allwinner,sun8i-a83t-sgx544-115 # Banana-Pi-M3 (Allwinner A83T) and similar + - const: img,sgx544-115 + - const: img,sgx544 + + - description: SGX544-116 based SoC + items: + - enum: + - ti,dra7-sgx544-116 # DRA7 + - ti,omap5-sgx544-116 # OMAP5 UEVM, Pyra Handheld and similar + - const: img,sgx544-116 + - const: img,sgx544 + + - description: SGX545 based SoC + items: + - const: intel,cedarview-gma3600-sgx545 # Atom N2600, D2500 + - const: img,sgx545-116 + - const: img,sgx545 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + items: + - const: sgx + + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + items: + - const: core + - const: sys + - const: mem + - const: hyd + + sgx-supply: true + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - |+ + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpu: gpu@fe00 { + compatible = "ti,omap5-sgx544-116", "img,sgx544-116", "img,sgx544"; + reg = <0xfe00 0x200>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; + +...
The Imagination PVR/SGX GPU is part of several SoC from multiple vendors, e.g. TI OMAP, Ingenic JZ4780, Intel Poulsbo, Allwinner A83 and others. With this binding, we describe how the SGX processor is interfaced to the SoC (registers and interrupt). The interface also consists of clocks, reset, power but information from data sheets is vague and some SoC integrators (TI) deciced to use a PRCM wrapper (ti,sysc) which does all clock, reset and power-management through registers outside of the sgx register block. Therefore all these properties are optional. Tested by make dt_binding_check Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> --- .../devicetree/bindings/gpu/img,pvrsgx.yaml | 150 ++++++++++++++++++ 1 file changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpu/img,pvrsgx.yaml