@@ -52,7 +52,10 @@ static int write_timestamp(struct i915_request *rq, int slot)
if (INTEL_GEN(rq->i915) >= 8)
cmd++;
*cs++ = cmd;
- *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
+ if (IS_GEN(rq->i915, 5) || IS_G4X(rq->i915))
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP_UDW(rq->engine->mmio_base));
+ else
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base));
*cs++ = i915_request_timeline(rq)->hwsp_offset + slot * sizeof(u32);
*cs++ = 0;
@@ -122,7 +125,8 @@ static int perf_mi_bb_start(void *arg)
enum intel_engine_id id;
int err = 0;
- if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ /* Do we have any CS_TIMESTAMP? */
+ if (INTEL_GEN(gt->i915) < 4)
return 0;
perf_begin(gt);
@@ -132,6 +136,14 @@ static int perf_mi_bb_start(void *arg)
u32 cycles[COUNT];
int i;
+ /*
+ * Do we have CS_TIMESTAMP for this engine?
+ * Despite what bspec says SNB does not have this
+ * for other engines.
+ */
+ if (INTEL_GEN(gt->i915) < 7 && id != RCS0)
+ continue;
+
intel_engine_pm_get(engine);
batch = create_empty_batch(ce);
@@ -246,7 +258,8 @@ static int perf_mi_noop(void *arg)
enum intel_engine_id id;
int err = 0;
- if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */
+ /* Do we have any CS_TIMESTAMP? */
+ if (INTEL_GEN(gt->i915) < 4)
return 0;
perf_begin(gt);
@@ -256,6 +269,14 @@ static int perf_mi_noop(void *arg)
u32 cycles[COUNT];
int i;
+ /*
+ * Do we have CS_TIMESTAMP for this engine?
+ * Despite what bspec says SNB does not have this
+ * for other engines.
+ */
+ if (INTEL_GEN(gt->i915) < 7 && id != RCS0)
+ continue;
+
intel_engine_pm_get(engine);
base = create_empty_batch(ce);