| Message ID | 20200515104758.6934-10-Sergey.Semin@baikalelectronics.ru (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | spi: dw: Add generic DW DMA controller support | expand |
On Fri, May 15, 2020 at 01:47:48PM +0300, Serge Semin wrote: > It isn't good to have numeric literals in the code especially if there > are multiple of them and they are related. Moreover in current > implementation the Tx DMA transfer activation level isn't optimal, > since it's hardwired to be at 16-32 bytes level, while it's better > to keep the SPI FIFO buffer as full as possible until all available > data is submitted. So lets introduce the DMA burst level > parametrization macros with optimal values - issue Rx transfer if at > least 16 bytes are available in the buffer and execute Tx transaction > if at least 16 bytes room is opened in SPI Tx FIFO. > - dw_writel(dws, DW_SPI_DMARDLR, 0xf); > - dw_writel(dws, DW_SPI_DMATDLR, 0x10); > + dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1); > + dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - TX_BURST_LEVEL); ...and if FIFO length is less than TX_BURST_LEVEL? For the patch that introduces definitions, i.e. keeping the last line here as dw_writel(dws, DW_SPI_DMATDLR, TX_BURST_LEVEL); I'm good. You may put your tag in that case. For fifo_len case we need to discuss in separate patch, perhaps.
On Sat, May 16, 2020 at 05:33:53PM +0300, Serge Semin wrote: > On Fri, May 15, 2020 at 05:01:29PM +0300, Andy Shevchenko wrote: > > On Fri, May 15, 2020 at 01:47:48PM +0300, Serge Semin wrote: > > > It isn't good to have numeric literals in the code especially if there > > > are multiple of them and they are related. Moreover in current > > > implementation the Tx DMA transfer activation level isn't optimal, > > > since it's hardwired to be at 16-32 bytes level, while it's better > > > to keep the SPI FIFO buffer as full as possible until all available > > > data is submitted. So lets introduce the DMA burst level > > > parametrization macros with optimal values - issue Rx transfer if at > > > least 16 bytes are available in the buffer and execute Tx transaction > > > if at least 16 bytes room is opened in SPI Tx FIFO. > > > > > - dw_writel(dws, DW_SPI_DMARDLR, 0xf); > > > - dw_writel(dws, DW_SPI_DMATDLR, 0x10); > > > + dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1); > > > + dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - TX_BURST_LEVEL); > > > > ...and if FIFO length is less than TX_BURST_LEVEL? > > > > For the patch that introduces definitions, i.e. keeping the last line here as > > > > dw_writel(dws, DW_SPI_DMATDLR, TX_BURST_LEVEL); > > > > I'm good. You may put your tag in that case. For fifo_len case we need to > > discuss in separate patch, perhaps. > > It's fixed in a consequent patch anyway. Though if v3 is required I'll remove > this change from here. I consider that here you might have introduced a regression and actually doing two things in one patch. Why not to split?
On Mon, May 18, 2020 at 02:01:50PM +0300, Andy Shevchenko wrote: > On Sat, May 16, 2020 at 05:33:53PM +0300, Serge Semin wrote: > > On Fri, May 15, 2020 at 05:01:29PM +0300, Andy Shevchenko wrote: > > > On Fri, May 15, 2020 at 01:47:48PM +0300, Serge Semin wrote: > > > > It isn't good to have numeric literals in the code especially if there > > > > are multiple of them and they are related. Moreover in current > > > > implementation the Tx DMA transfer activation level isn't optimal, > > > > since it's hardwired to be at 16-32 bytes level, while it's better > > > > to keep the SPI FIFO buffer as full as possible until all available > > > > data is submitted. So lets introduce the DMA burst level > > > > parametrization macros with optimal values - issue Rx transfer if at > > > > least 16 bytes are available in the buffer and execute Tx transaction > > > > if at least 16 bytes room is opened in SPI Tx FIFO. > > > > > > > - dw_writel(dws, DW_SPI_DMARDLR, 0xf); > > > > - dw_writel(dws, DW_SPI_DMATDLR, 0x10); > > > > + dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1); > > > > + dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - TX_BURST_LEVEL); > > > > > > ...and if FIFO length is less than TX_BURST_LEVEL? > > > > > > For the patch that introduces definitions, i.e. keeping the last line here as > > > > > > dw_writel(dws, DW_SPI_DMATDLR, TX_BURST_LEVEL); > > > > > > I'm good. You may put your tag in that case. For fifo_len case we need to > > > discuss in separate patch, perhaps. > > > > It's fixed in a consequent patch anyway. Though if v3 is required I'll remove > > this change from here. > > I consider that here you might have introduced a regression and actually doing > two things in one patch. Why not to split? Theoretically I could, but only for a hardware with FIFO smaller than 16 bytes. So did I, seeing this module has been dedicated for the Intel Medfield/Elkhart chips only? Anyway as I said this change is mostly redundant, since further in this patchset I'll replace the constants used here with burst length properly calculated based on the fifo-length and max-burst-length specific to the DMA. -Sergey > > -- > With Best Regards, > Andy Shevchenko > >
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c index ca8813a693d8..e43914dbcadf 100644 --- a/drivers/spi/spi-dw-mid.c +++ b/drivers/spi/spi-dw-mid.c @@ -20,7 +20,9 @@ #define WAIT_RETRIES 5 #define RX_BUSY 0 +#define RX_BURST_LEVEL 16 #define TX_BUSY 1 +#define TX_BURST_LEVEL 16 static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param) { @@ -193,7 +195,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws, memset(&txconf, 0, sizeof(txconf)); txconf.direction = DMA_MEM_TO_DEV; txconf.dst_addr = dws->dma_addr; - txconf.dst_maxburst = 16; + txconf.dst_maxburst = TX_BURST_LEVEL; txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; txconf.dst_addr_width = convert_dma_width(dws->n_bytes); txconf.device_fc = false; @@ -266,7 +268,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws, memset(&rxconf, 0, sizeof(rxconf)); rxconf.direction = DMA_DEV_TO_MEM; rxconf.src_addr = dws->dma_addr; - rxconf.src_maxburst = 16; + rxconf.src_maxburst = RX_BURST_LEVEL; rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; rxconf.src_addr_width = convert_dma_width(dws->n_bytes); rxconf.device_fc = false; @@ -291,8 +293,8 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer) { u16 imr = 0, dma_ctrl = 0; - dw_writel(dws, DW_SPI_DMARDLR, 0xf); - dw_writel(dws, DW_SPI_DMATDLR, 0x10); + dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1); + dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - TX_BURST_LEVEL); if (xfer->tx_buf) { dma_ctrl |= SPI_DMA_TDMAE;